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yosys/passes
Ben Widawsky 8767ec3fbd Add a few more filename rewrites
This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"

Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-20 10:27:59 -07:00
..
cmds Fixed the help summary line for a few commands 2019-06-19 15:27:04 -04:00
equiv Add -undef option to equiv_opt, passed to equiv_induct 2019-04-26 11:16:48 -07:00
fsm fsm_opt: Fix runtime error for FSMs without a reset state 2019-02-07 10:35:36 +00:00
hierarchy Use input default values in hierarchy pass 2019-06-19 11:49:20 +02:00
memory memory_bram: Fix multiport make_transp 2019-04-07 16:56:31 +01:00
opt Fix typo in opt_rmdff 2019-06-05 14:08:14 -07:00
pmgen Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 2019-05-28 17:17:56 +02:00
proc Improve proc full_case detection and handling, fixes #931 2019-04-18 15:13:47 +02:00
sat Add a few more filename rewrites 2019-06-20 10:27:59 -07:00
techmap Fix bug in #1078, add entry to CHANGELOG 2019-06-19 09:51:11 -07:00
tests flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00