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Author SHA1 Message Date
Eddie Hung
1f54b0008f
Merge pull request #1685 from dh73/gowin 
Removing cells_sim from GoWin bram techmap
 2020-02-06 20:59:21 -08:00
whitequark
6f67dd8df5
Merge pull request #1683 from whitequark/write_verilog-memattrs 
write_verilog: dump $mem cell attributes
 2020-02-07 02:54:04 +00:00
Marcin Kościelnicki
30854b9c7f xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
Marcin Kościelnicki
95c46ccc55 xilinx: Add support for Spartan 3A DSP block RAMs. 
Part of #1550
 2020-02-07 01:00:29 +01:00
Eddie Hung
1784d25f53
Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map 
Fix/cleanup +/xilinx/arith_map.v
 2020-02-06 13:51:23 -08:00
Diego H
87883f6d88 Removing cells_sim.v from bram techmap pass 2020-02-06 14:38:29 -06:00
Eddie Hung
d625e399cb Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk 2020-02-06 11:25:07 -08:00
Eddie Hung
5ecbc6c7b2 Fix/cleanup +/xilinx/arith_map.v 2020-02-06 11:00:04 -08:00
Marcin Kościelnicki
8f559b070a edif: more resilience to mismatched port connection sizes. 
Fixes #1653.
 2020-02-06 18:45:03 +01:00
whitequark
e95a8ba763 write_verilog: dump $mem cell attributes. 
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
 2020-02-06 16:22:42 +00:00
Rodrigo Alejandro Melo
9da5936c05 Added 'set -e' into tests/memfile/run-test.sh 
Also added two checks for situations where the execution must fail.

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-06 10:45:40 -03:00
Rodrigo Alejandro Melo
da485dc007 Modified $readmem[hb] to use '\' or '/' according the OS 
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-06 10:10:29 -03:00
Eddie Hung
d44848328b
Merge pull request #1682 from YosysHQ/eddie/opt_after_techmap 
synth_*: call 'opt -fast' after 'techmap'
 2020-02-05 20:21:40 -08:00
Eddie Hung
0b0148399c synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
Eddie Hung
fc33287bc1 verilog: instead of modifying localparam size, extend init constant expr 2020-02-05 17:19:42 -08:00
Eddie Hung
4c1d3a126d shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
Eddie Hung
505557e93e
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init 
opt_merge: discard \init of '$' cells with 'Q' port when merging
 2020-02-05 14:56:26 -08:00
Eddie Hung
6eb7e925a1
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux 
techmap LSB-first for compatible $shift/$shiftx cells
 2020-02-05 14:55:57 -08:00
Eddie Hung
0b308c6835 abc9_ops: -reintegrate to use derived_type for box_ports 2020-02-05 14:46:48 -08:00
Eddie Hung
b6a1f627b5 Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
Eddie Hung
5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631 
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
 2020-02-05 19:31:18 +01:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required 
abc9: add support for required times
 2020-02-05 18:59:40 +01:00
Stefan Biereigel
90c78f1f85 add testcase for #1614 2020-02-03 21:29:54 +01:00
Stefan Biereigel
b844b078db correct wire declaration grammar for #1614 2020-02-03 21:29:40 +01:00
Stefan Biereigel
3d13b10859 remove namespace mention from inheritance information 2020-02-03 20:54:32 +01:00
Stefan Biereigel
362e3aa40f expose polymorphism through python wrappers 2020-02-03 20:21:02 +01:00
Rodrigo A. Melo
665a967d87
Merge branch 'master' into master 2020-02-03 11:07:51 -03:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Rodrigo Alejandro Melo
313a425bd5 Merge branch 'master' of https://github.com/YosysHQ/yosys 
Solved a conflict into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:56:41 -03:00
Rodrigo Alejandro Melo
71f3afb9a2 Replaced strlen by GetSize into simplify.cc 
As recommended in CodingReadme.

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:44:09 -03:00
David Shah
7033503cd9
Merge pull request #1516 from YosysHQ/dave/dotstar 
sv: Add support for wildcard port connections (.*)
 2020-02-02 18:12:28 +00:00
David Shah
0488492ad2 Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:13:13 +00:00
David Shah
4bfd2ef4f3 sv: Improve handling of wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
ebe1d7d5ab sv: More tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
7e741714df hierarchy: Correct handling of wildcard port connections with default values 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
a210675d71 sv: Add tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
5df591c023 hierarchy: Resolve SV wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
50f86c11b2 sv: Add lexing and parsing of .* (wildcard port conns) 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
Rodrigo Alejandro Melo
8217f579b7 Removed 'synth' into tests/memfile/run-test.sh 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-02 12:34:27 -03:00
Rodrigo Alejandro Melo
9b49f1bc46 Added content1.dat into tests/memfile 
Modified run-test.sh to use it.

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-02 12:18:34 -03:00
David Shah
9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf 
ast: Add support for $sformatf system function
 2020-02-02 14:53:46 +00:00
David Shah
1055b6b1dd
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly 
synth_xilinx: add -dsp-multonly
 2020-02-02 14:53:32 +00:00
Marcin Kościelnicki
b44d0e041f xilinx: use RAM32M/RAM64M for memories with two read ports 
This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
 2020-02-02 14:34:21 +01:00
Rodrigo Alejandro Melo
2774aae0f2 Removed a line jump into the CHANGELOG 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 22:56:01 -03:00
Rodrigo Alejandro Melo
eaaba6e091 Added tests/memfile to 'make test' with an extra testcase 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 22:44:06 -03:00
Rodrigo Alejandro Melo
43396fae2c Added a test for the Memory Content File inclusion using $readmemb 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 17:41:10 -03:00
Rodrigo Alejandro Melo
b4c30cfc8d Fixed a bug in the new feature of $readmem[hb] when an empty string is provided 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 17:03:56 -03:00
David Shah
65716c9982 xilinx_dsp: Add multonly scratchpad var to bypass 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-01 15:30:43 +00:00
Marcin Kościelnicki
00fba62711 json: remove the 32-bit parameter special case 
Before, the rules for encoding parameters in JSON were as follows:

- if the parameter is not a string:

  - if it is exactly 32 bits long and there are no z or x bits, emit it
    as an int
  - otherwise, emit it as a string made of 0/1/x/z characters

- if the parameter is a string:

  - if it contains only 0/1/x/z characters, append a space at the end
    to distinguish it from a non-string
  - otherwise, emit it directly

However, this caused a problem in the json11 parser used in nextpnr:
yosys emits unsigned ints, and nextpnr parses them as signed, using
the value of INT_MIN for values that overflow the signed int range.
This caused destruction of LUT5 initialization values.  Since both
nextpnr and yosys parser can also accept 32-bit parameters in the
same encoding as other widths, let's just remove that special case.
The old behavior is still left behind a `-compat-int` flag, in case
someone relies on it.
 2020-02-01 16:16:26 +01:00
Eddie Hung
136842b1ef Merge branch 'master' into eddie/submod_po 2020-02-01 02:14:19 -08:00