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Code Activity
3836 commits 122 branches 59 tags 73 MiB
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666 commits

Author SHA1 Message Date
Jim Paris
4a229e5b95 Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
Jim Paris
872d8d49e9 Skip spaces around macro arguments 2018-05-17 00:06:49 -04:00
Clifford Wolf
a7281930c5 Fix handling of anyconst/anyseq attrs in VHDL code via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 19:27:00 +02:00
Sergiusz Bazanski
7d076f071e Also interpret '&' in liberty functions 2018-05-12 20:55:31 +02:00
Clifford Wolf
24e6401617 Further improve handling of zero-length SVA consecutive repetition 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-05 14:32:04 +02:00
Clifford Wolf
3e67497ec2 Fix handling of zero-length SVA consecutive repetition 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-05 13:58:01 +02:00
Clifford Wolf
a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Dan Gisselquist
e060375f23 Support more character literals 2018-05-03 12:35:01 +02:00
Clifford Wolf
2d7f3123f0 Add statement labels for immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-13 11:52:28 +02:00
Clifford Wolf
66ffc99695 Allow "property" in immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-12 14:28:28 +02:00
Clifford Wolf
617c60cea6 Add PRIM_HDL_ASSERTION support to Verific importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-07 18:38:42 +02:00
Clifford Wolf
0ac768f9df Fix handling of $global_clocking in Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 21:23:47 +02:00
Clifford Wolf
5ea2c53604 Add read_verilog anyseq/anyconst/allseq/allconst attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:35:11 +02:00
Clifford Wolf
278685b084 Add Verific anyseq/anyconst/allseq/allconst attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:19:55 +02:00
Clifford Wolf
ab8db2c168 Add "verific -autocover" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:10:57 +02:00
makaimann
0c404b1f63 Set RAM runtime flags for Verific frontend 2018-04-05 17:38:08 -07:00
Clifford Wolf
93985d91b1 Remove left-over log_ping debug commands.. oops. 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-31 14:23:57 +02:00
Udi Finkelstein
6378e2cd46 First draft of Verilog parser support for specify blocks and parameters. 
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
 2018-03-27 14:34:00 +02:00
Clifford Wolf
315d5e32bf Fix handling of unclocked immediate assertions in Verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-26 13:04:10 +02:00
Clifford Wolf
e7862d4f64 Update todo for more features to verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-16 15:48:48 +01:00
Clifford Wolf
38596ce68f Update todo for more features to verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-16 12:16:52 +01:00
Clifford Wolf
462e9f7bd4 Add todo for more features to verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-16 12:15:36 +01:00
Clifford Wolf
7cf9d88028 Improve import of memories via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-15 18:20:37 +01:00
Clifford Wolf
bf402a806a Fix handling of SV compilation units in Verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-14 20:22:11 +01:00
Clifford Wolf
307c16a309 Fix SVA handling of NON_CONSECUTIVE_REPEAT and GOTO_REPEAT 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 16:24:01 +01:00
Clifford Wolf
ce37b6d730 Fix variable name typo in verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 14:33:42 +01:00
Clifford Wolf
da216937b1 Add support for trivial SVA sequences and properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 14:32:01 +01:00
Clifford Wolf
a15208f301 Use Verific hier_tree component for elaboration 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-08 13:26:33 +01:00
Clifford Wolf
a4bbfd2d15 Fix Verific handling of "assert property (..);" in always block 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-07 20:06:02 +01:00
Clifford Wolf
92d5f4db6f Add "verific -import -V" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-07 19:40:34 +01:00
Clifford Wolf
252627fc54 Set Verific db_preserve_user_nets flag 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-07 18:08:03 +01:00
Clifford Wolf
dcc4a18d5a Update comment about supported SVA in verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 15:47:33 +01:00
Clifford Wolf
03b49654b1 Add SVA NON_CONSECUTIVE_REPEAT and GOTO_REPEAT support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 15:39:46 +01:00
Clifford Wolf
7bb83ae9f2 Add SVA first_match() support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 15:06:35 +01:00
Clifford Wolf
78f2cca2d9 Add SVA within support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 14:41:27 +01:00
Clifford Wolf
5555292ce2 Add support for SVA sequence intersect 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 14:26:57 +01:00
Clifford Wolf
d86e875f0f Add get_fsm_accept_reject for parsing SVA properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 11:50:38 +01:00
Clifford Wolf
588ce0e34a Simplified SVA "until" handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 01:51:42 +01:00
Clifford Wolf
480e8e676a Add proper SVA seq.triggered support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 19:29:26 +01:00
Clifford Wolf
8dcf3d0c76 Add Verific SVA support for "seq and seq" expressions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 15:08:21 +01:00
Clifford Wolf
9ab2498c55 Refactor Verific SVA importer property parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 14:29:48 +01:00
Clifford Wolf
261cf706f4 Add VerificClocking class and refactor Verific DFF handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 13:48:53 +01:00
Clifford Wolf
707ddb77bc Add SVA support for sequence OR 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-03 16:34:28 +01:00
Clifford Wolf
cabc3c59e0 Fix handling of SVA "until seq.triggered" properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-02 18:17:10 +01:00
Clifford Wolf
ab791e61b3 Update SVA cheat sheet in verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-02 16:05:56 +01:00
Clifford Wolf
4e5f1f59d6 Fix in Verific SVA importer handling of until_with 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-01 19:37:36 +01:00
Clifford Wolf
9a2a8cd97b Fixes and improvements in Verific SVA importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-01 11:40:43 +01:00
Clifford Wolf
3c49e3c5b3 Add $rose/$fell support to Verific bindings 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-01 10:12:15 +01:00
Clifford Wolf
5ac3ee858a Add support for PRIM_SVA_UNTIL to new SVA importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-28 15:32:17 +01:00
Clifford Wolf
8a1d6ccf0c Add DFSM generator to verific SVA importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-28 15:05:33 +01:00