Clifford Wolf 278685b084 Add Verific anyseq/anyconst/allseq/allconst attribute support ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2018-04-06 14:19:55 +02:00
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ast	Add $allconst and $allseq cell types	2018-02-23 13:14:47 +01:00
blif	Increase maximum LUT size in blifparse to 12 bits	2017-09-27 15:27:42 +02:00
ilang	Added avail params to ilang format, check module params in 'hierarchy -check'	2016-10-22 11:05:49 +02:00
json	Parse reals as string in JSON front-end	2017-09-26 14:37:03 +02:00
liberty	Improve handling of "bus" pins in liberty front-end (some files use bus.pin.direction)	2018-02-15 17:36:08 +01:00
verific	Add Verific anyseq/anyconst/allseq/allconst attribute support	2018-04-06 14:19:55 +02:00
verilog	First draft of Verilog parser support for specify blocks and parameters.	2018-03-27 14:34:00 +02:00