George Rennie
ff6c9446c0
bufnorm: preserve constant bits when mapping back to connections
2024-11-12 01:05:15 +01:00
Martin Povišer
1b1a6c4aed
Merge pull request #4525 from georgerennie/peepopt_clock_gate
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peepopt: Add formal opt to rewrite latches to ffs in clock gates
2024-11-11 14:49:09 +01:00
mszelwiga
8e508f2a2a
Fix setting bits of parameters in setundef pass
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This commit also adds test that verifies correctness of this change.
2024-11-08 17:03:08 +01:00
George Rennie
8f6058a7d6
bufnorm: preserve constant bits driving wires
2024-11-07 11:48:48 +01:00
George Rennie
626dbbe1e0
proc_dff: fix early return bug
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* early return caused proc_dff to stop considering rules after seeing
one async rule - this is because continue should have been used to
continue to procecssing the next rule instead of returning from the
function
2024-11-07 00:06:03 +01:00
Emil J. Tywoniak
387a235158
functional, glift: use fold overload of IdString::in instead of pool literals
2024-11-06 12:48:32 +01:00
Martin Povišer
29af057430
Merge pull request #4707 from povik/stat-unused
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stat: Drop unused field
2024-11-05 09:38:29 +01:00
Martin Povišer
4df3a5d7ec
stat: Drop unused field
2024-11-05 09:37:35 +01:00
Martin Povišer
c8fffce2b5
keep_hierarchy: Update messages
2024-11-05 09:03:01 +01:00
Martin Povišer
cf79630be0
keep_hierarchy: Require size information on blackboxes
2024-11-05 09:02:36 +01:00
Martin Povišer
2425352551
keep_hierarchy: Redo hierarchy traversal for -min_cost
2024-11-05 09:02:36 +01:00
Lofty
3250f2b82b
Merge pull request #4700 from povik/select-list-mod
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Add `select -list-mod`
2024-11-04 15:38:42 +00:00
Martin Povišer
cbe73c9047
cellmatch: Visit whiteboxes for -derive_luts
2024-11-04 14:28:46 +01:00
Martin Povišer
c9ed6d8dcf
cellmatch: Rename -lut_attrs to -derive_luts; document option
2024-11-04 14:28:40 +01:00
Martin Povišer
35a20da512
logger: Adjust print
2024-11-04 13:16:40 +01:00
Martin Povišer
7aa3fdab80
select: Add -list-mod option
2024-11-04 13:16:13 +01:00
Lofty
dd7ea0ab6c
qwp: remove
2024-10-25 14:09:58 +01:00
Martin Povišer
9432e972f7
Merge pull request #4626 from povik/select-t-at
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select: Add new `t:@<name>` syntax
2024-10-16 10:18:05 +02:00
Martin Povišer
09be0351ce
select: Add new t:@<name> syntax
2024-10-15 12:22:02 +02:00
Emil J. Tywoniak
785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
Martin Povišer
a00137c2f6
Merge pull request #4625 from povik/cellmatch-lut
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cellmatch: Size the `lut` attribute
2024-10-11 14:08:55 +02:00
KrystalDelusion
0be3b7de51
Merge pull request #4635 from YosysHQ/krys/pr_docs_ci
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Remove make docs race conditions (and other docs fixes)
2024-10-08 21:39:30 +13:00
Miodrag Milanovic
f079772ade
Add TODO for missing help messages
2024-10-08 08:47:51 +02:00
Martin Povišer
9479d3bd3c
Merge pull request #4637 from YosysHQ/emil/bufnorm-warning
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bufnorm: avoid warning. NFC
2024-10-07 18:01:42 +02:00
Emil J. Tywoniak
a76bcdc58f
bufnorm: avoid remove warning. NFC
2024-10-07 17:58:48 +02:00
Martin Povišer
74e92d10e8
Merge pull request #4593 from povik/aiger2
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New aiger backend
2024-10-07 16:11:25 +02:00
Martin Povišer
2e587c835f
abc9_exe: Document SC mapping options
2024-10-07 12:03:49 +02:00
Martin Povišer
3b6dcc7bd0
abc9_exe: Remove -genlib option
2024-10-07 12:03:49 +02:00
Martin Povišer
e0a86d5483
abc_new: Start new command for aiger2-based round trip
2024-10-07 12:03:49 +02:00
Martin Povišer
e58a9b6ab6
abc9: Understand ASIC options similar to abc
2024-10-07 12:03:48 +02:00
Martin Povišer
ec42b42bd9
cellmatch: Size the lut attribute
2024-10-02 11:29:54 +02:00
George Rennie
023f029dcf
opt_reduce: keep at least one input to $reduce_or/and cells
2024-09-25 16:21:19 +01:00
George Rennie
58af70624f
opt_demorgan: skip zero width cells
2024-09-24 14:24:59 +01:00
N. Engelhardt
8e1e2b9a39
Merge pull request #4495 from povik/check-avert-costly-detail
2024-09-23 15:19:48 +02:00
Martin Povišer
38de01807e
Mark bufnorm experimental
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
80119386c0
Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
8bb70bac8d
Improvements in "bufnorm" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
d027ead4b5
Improvements in "bufnorm" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
f4b7ea5fb3
Improvements in "bufnorm" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
32808a0393
Improvements and fixes to "bufnorm" cmd
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
d0b5dfa6ef
Add bufnorm pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Emil J
52382c6544
Merge pull request #4583 from YosysHQ/emil/clock_gate
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clockgate: centralize clock enables out of FFs
2024-09-16 15:41:01 +02:00
Emil J. Tywoniak
f193bcf683
clockgate: help string
2024-09-16 14:20:33 +02:00
Emil J. Tywoniak
be7c93ec6d
clockgate: 1-bit const 0
2024-09-16 13:58:27 +02:00
Emil J
a8a92d3469
clockgate: help string
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Co-authored-by: Martin Povišer <povik@cutebit.org>
2024-09-16 13:55:53 +02:00
N. Engelhardt
c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds
2024-09-12 13:04:04 +02:00
Emil J. Tywoniak
1e999a3cb7
clockgate: EN can be a bit on a multi-bit wire
2024-09-11 19:18:25 +02:00
Martin Povišer
34572708d5
Merge pull request #4595 from YosysHQ/emil/internal_stats-astnode
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internal_stats: astnode (sizeof)
2024-09-11 12:21:29 +02:00
Emil J. Tywoniak
1372c47036
internal_stats: astnode (sizeof)
2024-09-11 11:34:20 +02:00
Emil J. Tywoniak
8b464341c2
clockgate: no initvals
2024-09-11 10:24:48 +02:00
