mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity
6196 commits 122 branches 59 tags 73 MiB
Commit graph

6196 commits

This branch
This branch
All branches
Author SHA1 Message Date
Clifford Wolf
9d6586b4e1
Merge pull request #933 from dh73/master 
Fixing issues in CycloneV cell sim
 2019-04-12 14:57:36 +02:00
Clifford Wolf
48bc203653
Merge pull request #932 from YosysHQ/eddie/fixdlatch 
Recognise default entry in case even if all cases covered (fix for #931)
 2019-04-12 14:57:01 +02:00
Diego
643ae9bfc5 Fixing issues in CycloneV cell sim 2019-04-11 19:59:03 -05:00
Eddie Hung
3c1f1a6605 Fix ordering of when to insert zero index 2019-04-11 16:25:59 -07:00
Eddie Hung
53513c52df Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux 2019-04-11 16:21:01 -07:00
Eddie Hung
f587950bde More unused 2019-04-11 16:20:43 -07:00
Eddie Hung
35181a7866 Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux 2019-04-11 16:18:45 -07:00
Eddie Hung
b15b410b41 Remove unused 2019-04-11 16:18:01 -07:00
Eddie Hung
b1f1db2fcf Fixes 2019-04-11 16:17:09 -07:00
Eddie Hung
e8c26f2839 WIP 2019-04-11 15:52:04 -07:00
Eddie Hung
09e7eb7aed Spelling fixes 2019-04-11 15:09:13 -07:00
Eddie Hung
7685469ee2 Add default entry to testcase 2019-04-11 15:03:40 -07:00
Eddie Hung
adc6efb584 Recognise default entry in case even if all cases covered (#931) 2019-04-11 12:34:51 -07:00
Eddie Hung
233edf00fe Fix cells_map.v some more 2019-04-11 10:48:14 -07:00
Eddie Hung
8658b56a08 More fine tuning 2019-04-11 10:08:05 -07:00
Eddie Hung
0ec8564099 Fix cells_map.v 2019-04-11 10:04:58 -07:00
Eddie Hung
bca3779657 Fix typo 2019-04-11 09:25:19 -07:00
Eddie Hung
87b8d29a90 Juggle opt calls in synth_xilinx 2019-04-11 09:13:39 -07:00
Eddie Hung
227cc54c16 Merge branch 'xaig' into xc7mux 2019-04-10 18:07:11 -07:00
Eddie Hung
2217d59e29 Add non-input bits driven by unrecognised cells as ci_bits 2019-04-10 18:06:33 -07:00
Eddie Hung
cd7b2de27f WIP for cells_map.v -- maybe working? 2019-04-10 18:05:09 -07:00
Eddie Hung
3d577586fd Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 2019-04-10 16:15:23 -07:00
Eddie Hung
3f5dab0d09 Fix for when B_SIGNED = 1 2019-04-10 14:51:10 -07:00
Eddie Hung
32561332b2 Update doc for synth_xilinx 2019-04-10 14:48:58 -07:00
Eddie Hung
bf92218e0f Merge branch 'xaig' into xc7mux 2019-04-10 14:03:09 -07:00
Eddie Hung
1a49cf29d8 parse_aiger() to rename all $lut cells after "clean" 2019-04-10 14:02:23 -07:00
Eddie Hung
17a02df05c ff_map.v after abc 2019-04-10 12:36:06 -07:00
Eddie Hung
1ec949d5ed Tidy up 2019-04-10 09:02:42 -07:00
Eddie Hung
526aef9c2a Move map_cells to before map_luts 2019-04-10 08:50:31 -07:00
Eddie Hung
e0b46eb4cb WIP for $shiftx to wide mux 2019-04-10 08:49:55 -07:00
Eddie Hung
4dac9818bd Update LUT delays 2019-04-10 08:49:39 -07:00
Eddie Hung
9a6da9a79a synth_* with -retime option now calls abc with -D 1 as well 2019-04-10 08:32:53 -07:00
Eddie Hung
5f4024ffd2 Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen" 
This reverts commit 19271bd996.
 2019-04-10 08:31:40 -07:00
Eddie Hung
78d35a86c0 Revert ""&nf -D 0" fails => use "-D 1" instead" 
This reverts commit 3c253818ca.
 2019-04-10 08:31:35 -07:00
Eddie Hung
c89cd48f58 Merge remote-tracking branch 'origin/master' into eddie/fix_retime 2019-04-10 08:23:00 -07:00
Eddie Hung
3e368593eb Add cells.lut to techlibs/xilinx/ 2019-04-09 14:33:37 -07:00
Eddie Hung
fd88ab5c83 synth_xilinx to call abc with -lut +/xilinx/cells.lut 2019-04-09 14:32:39 -07:00
Eddie Hung
b9e19071b8 Add delays to cells.box 2019-04-09 14:32:10 -07:00
Eddie Hung
d536379c62 Add "-lut <file>" support to abc9 2019-04-09 14:31:31 -07:00
Jim Lawson
354ba5ba83 Merge remote-tracking branch 'upstream/master' 2019-04-09 13:41:58 -07:00
Keith Rothman
e107ccdde8 Fix LUT6_2 definition. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 11:43:19 -07:00
Eddie Hung
f2042fc7c4 synth_xilinx with abc9 to use -box 2019-04-09 11:01:46 -07:00
Eddie Hung
2ae26b986c Add techlibs/xilinx/cells.box 2019-04-09 10:58:58 -07:00
Eddie Hung
7e304c362b Add "-box" option to abc9 2019-04-09 10:58:06 -07:00
Eddie Hung
bd523abef5 Add 'setundef -zero' call prior to aigmap in abc9 2019-04-09 10:32:58 -07:00
Eddie Hung
3b6f85b0a6 Comment out 2019-04-09 10:09:43 -07:00
Eddie Hung
3fc474aa73 Add support for synth_xilinx -abc9 and ignore abc9 -dress opt 2019-04-09 10:06:44 -07:00
Zachary Snow
5855024ccc support repeat loops with constant repeat counts outside of constant functions 2019-04-09 12:28:32 -04:00
Keith Rothman
5e0339855f Add additional cells sim models for core 7-series primatives. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 09:01:53 -07:00
Eddie Hung
0deaccbaae
Fix a few typos 2019-04-08 16:46:33 -07:00