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6566 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Clifford Wolf
5c933e5110
Merge pull request #1218 from ZirconiumX/synth_intel_iopads 
intel: Make -noiopads the default
 2019-07-25 17:19:54 +02:00
Clifford Wolf
2bdd8003d3
Merge pull request #1219 from jakobwenzel/objIterator 
made ObjectIterator comply with Iterator Interface
 2019-07-25 17:19:11 +02:00
Eddie Hung
5248a902ef
Merge pull request #1224 from YosysHQ/xilinx_fix_ff 
xilinx: Fix missing cell name underscore in cells_map.v
 2019-07-25 06:44:17 -07:00
Jakob Wenzel
70882a8070 replaced std::iterator with using statements 2019-07-25 09:51:09 +02:00
David Shah
ab607e896e xilinx: Fix missing cell name underscore in cells_map.v 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-25 08:19:07 +01:00
Jim Lawson
7e298084e4 Call log_error() instead of log_warning() on unsupported cell type in FIRRTL backend. 2019-07-24 13:33:16 -07:00
Eddie Hung
d6a289d3e3
Merge pull request #1222 from koriakin/s6-example 
Add a simple example for Spartan 6
 2019-07-24 10:51:03 -07:00
Jim Lawson
c66b7402c0 Merge remote-tracking branch 'upstream/master' 2019-07-24 10:20:46 -07:00
Marcin Kościelnicki
173c975894 Add a simple example for Spartan 6 2019-07-24 18:59:03 +02:00
Jakob Wenzel
25685a9a5b made ObjectIterator extend std::iterator 
this makes it possible to use std algorithms on them
 2019-07-24 16:35:40 +02:00
Dan Ravensloft
49528ed3bd intel: Make -noiopads the default 2019-07-24 10:38:15 +01:00
Dan Ravensloft
67b4ce06e0 intel: Map M9K BRAM only on families that have it 
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
 2019-07-23 18:11:11 +01:00
Eddie Hung
a66f17b6a7
Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp 
ice40: Fix SB_MAC16 sim model for signed modes
 2019-07-23 09:56:58 -07:00
Eddie Hung
280288a62a Update changelog 2019-07-22 07:46:06 -07:00
Eddie Hung
be3d9c8eaa
Merge pull request #1214 from jakobwenzel/astmod_clone 
initialize noblackbox and nowb in AstModule::clone
 2019-07-22 07:42:53 -07:00
Jakob Wenzel
e2fe8e0a4f initialize noblackbox and nowb in AstModule::clone 2019-07-22 10:37:40 +02:00
Clifford Wolf
c6d8692c97 Add "stat -tech cmos" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-20 15:06:28 +02:00
Eddie Hung
09beeee38a Try and fix again 2019-07-19 14:40:57 -07:00
Eddie Hung
c926eeb43a Add another test 2019-07-19 14:02:46 -07:00
Eddie Hung
cb0fd05215 Do not access beyond bounds 2019-07-19 13:58:50 -07:00
Eddie Hung
54708dfbd7 Add an SigSpec::at(offset, defval) convenience method 2019-07-19 13:54:57 -07:00
Eddie Hung
3a87dc3524 Wrap A and B in sigmap 2019-07-19 13:23:07 -07:00
Eddie Hung
31b0002e8c Remove "top" from message 2019-07-19 13:20:45 -07:00
Eddie Hung
bcd8027182 Also optimise MSB of $sub 2019-07-19 13:11:48 -07:00
Eddie Hung
5bd088a686 Add one more test with trimming Y_WIDTH of $sub 2019-07-19 13:11:30 -07:00
Eddie Hung
415a2716df Be more explicit 2019-07-19 12:53:18 -07:00
Eddie Hung
fc0e36d1c0 wreduce for $sub 2019-07-19 12:50:21 -07:00
Eddie Hung
4e9b1d36fa Add tests for sub too 2019-07-19 12:50:11 -07:00
Eddie Hung
3839bd50f2 Add test 2019-07-19 12:43:02 -07:00
Eddie Hung
25ff27e37f SigSpec::extract to take negative lengths 2019-07-19 12:34:04 -07:00
David Shah
80884d6f7b ice40: Fix test_dsp_model.sh 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:57 +01:00
David Shah
79f14c7514 ice40/cells_sim.v: Fix sign of J and K partial products 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:41 +01:00
David Shah
3c84271543 ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:13:34 +01:00
Eddie Hung
171cd2ff73 Add tests for all combinations of A and B signedness for comb mul 2019-07-19 08:52:49 -07:00
Eddie Hung
f7753720fe Don't copy ref if exists already 2019-07-19 08:45:35 -07:00
Eddie Hung
43616e1414 Update Makefile too 2019-07-18 14:51:55 -07:00
Eddie Hung
4b71e6c421 Add CHANGELOG entry 2019-07-18 14:21:04 -07:00
Eddie Hung
b97fe6e866 Work in progress for renaming labels/options in synth_xilinx 2019-07-18 14:20:43 -07:00
David Shah
9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups 
Assorted synth_intel cleanups from @bwidawsk
 2019-07-18 19:04:28 +01:00
Dan Ravensloft
0c999ac2c4 synth_intel: Use stringf 2019-07-18 19:02:23 +01:00
David Shah
8e0f7c18f1
Merge pull request #1207 from ZirconiumX/intel_new_pass_names 
synth_intel: rename for consistency with #1184
 2019-07-18 17:34:55 +01:00
Dan Ravensloft
50f5e29724 synth_intel: s/not family/no family/ 2019-07-18 17:28:21 +01:00
Dan Ravensloft
d5b3b3bc6f synth_intel: revert change to run_max10 2019-07-18 17:09:15 +01:00
Ben Widawsky
999811572a intel_synth: Fix help message 
cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.

Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:25 +01:00
Ben Widawsky
f950a7a75d intel_synth: Small code cleanup to remove if ladder 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:12 +01:00
Ben Widawsky
809b94a67b intel_synth: Make family explicit and match 
The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:03 +01:00
Ben Widawsky
060e77c09b intel_synth: Minor code cleanups 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:05:54 +01:00
Dan Ravensloft
c78ab8ebc5 synth_intel: rename for consistency with #1184 
Also fix a typo in the help message.
 2019-07-18 16:46:21 +01:00
Clifford Wolf
e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels 
synth_{ice40,ecp5}: more sensible pass label naming
 2019-07-18 15:34:28 +02:00
Clifford Wolf
927f0caa9d
Merge pull request #1203 from whitequark/write_verilog-zero-width-values 
write_verilog: dump zero width constants correctly
 2019-07-18 15:31:27 +02:00