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Merge pull request #1207 from ZirconiumX/intel_new_pass_names

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synth_intel: rename for consistency with #1184
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David Shah 2019-07-18 17:34:55 +01:00 committed by GitHub
parent e66e8fb59d c78ab8ebc5
commit 8e0f7c18f1
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GPG key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 4 deletions
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8
techlibs/intel/synth_intel.cc
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@ -62,10 +62,10 @@ struct SynthIntelPass : public ScriptPass {
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -noiopads\n");
log(" do not use altsyncram cells in output netlist\n");
log(" do not use IO pad cells in output netlist\n");
log("\n");
log(" -nobram\n");
log(" do not use altsyncram cells in output netlist\n");
log(" do not use block RAM cells in output netlist\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis\n");
@ -191,12 +191,12 @@ struct SynthIntelPass : public ScriptPass {
run("synth -run coarse");
}
if (!nobram && check_label("bram", "(skip if -nobram)")) {
if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
run("memory_bram -rules +/intel/common/brams.txt");
run("techmap -map +/intel/common/brams_map.v");
}
if (check_label("fine")) {
if (check_label("map_ffram")) {
run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map");
run("opt -undriven -fine");