Charlotte
992a728ec7
tests: CXX may be e.g. gcc, so use CC and link stdc++ explicitly
2023-08-11 04:46:52 +02:00
Charlotte
4e94f62116
simlib: blackbox $print cell
...
It's possible to `generate` the appropriate always blocks per the
triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter.
2023-08-11 04:46:52 +02:00
Charlotte
fc0acd0ad1
cxxrtl: restrict -print-output to cout, cerr
2023-08-11 04:46:52 +02:00
Charlotte
f9b149fa7b
cxxrtl: add "-print-output" option, test in fmt
2023-08-11 04:46:52 +02:00
Charlotte
bfa8b631bf
cxxrtl: remove unused signedDivideWithRemainder
2023-08-11 04:46:52 +02:00
Charlotte
a1de898fcc
fmt: merge fuzzers since we don't rely on BigInteger logic
...
This is per fmt's (effective) use, as it turns out, so we're not losing
any fidelity in the comparison.
2023-08-11 04:46:52 +02:00
Charlotte
3571bf2c2d
fmt: fuzz, remove some unnecessary busywork
...
Removing some signed checks and logic where we've already guaranteed the
values to be positive. Indeed, in these cases, if a negative value got
through (per my realisation in the signed fuzz harness), it would cause
an infinite loop due to flooring division.
2023-08-11 04:46:52 +02:00
Charlotte
2ae551c0af
fmt: fuzz, fix (remove extraneous + incorrect fill)
...
"blk + chunks" is often an overrun, plus the fill is unnecessary; we
throw blk away immediately.
2023-08-11 04:46:52 +02:00
Charlotte
9f9561379b
fmt: format %t consistently at initial
2023-08-11 04:46:52 +02:00
Charlotte
c391ee7a0d
docs: document simulation time format specifiers
2023-08-11 04:46:52 +02:00
Charlotte
75b44f21d1
fmt: rudimentary %m support (= %l)
2023-08-11 04:46:52 +02:00
Charlotte
c382d7d3ac
fmt: %t/$time support
2023-08-11 04:46:52 +02:00
Charlotte
52dc397a50
cxxrtl: don't use signed divide with unsigned/pos values
...
Incorrect for unsigned, wasted effort for positive signed.
2023-08-11 04:46:52 +02:00
Charlotte
b0f69f2cd5
tests: test cxxrtl against iverilog (and uncover bug!)
2023-08-11 04:46:52 +02:00
Charlotte
095b093f4a
cxxrtl: first pass of $print impl
2023-08-11 04:46:52 +02:00
Charlotte
202c3776e2
docs: elaborate $print documentation
2023-08-11 04:46:52 +02:00
Charlotte
d9e4582558
fmt: handle part with unspecified padding in emit_rtlil
...
e.g. `$displayh(8'ha)` won't have a padding set, because it just gets
`lzero` set instead by `compute_required_decimal_places`.
It also doesn't have a width. In this case, we can just fill in a dummy
(unused) padding. Either space or zero would work, but space is a bit
more distinct given the width field follows.
Also omit writing the width if it's zero. This makes the emitted ilang
a little cleaner in places; `{8:> h0u}` is the output for this example,
now. The other possible extreme would be `{8:>00h0u}`.
2023-08-11 04:46:52 +02:00
Charlotte
1a222cb163
fmt: function name typo
2023-08-11 04:46:52 +02:00
Charlotte
2d7b8f71cc
docs: first pass $print documentation
2023-08-11 04:46:52 +02:00
Charlotte
289f8d42cb
fmt: correct parsing of {{ and }} for brace literals
2023-08-11 04:46:52 +02:00
Charlotte
3c8f84b70b
fmt: fix another overrun
2023-08-11 04:46:52 +02:00
Charlotte
28bd3a4b5d
fmt: don't overrun fmt string buffer
...
For input like "{", "{1", etc., we would exit the loop due to
`i < fmt.size()` no longer being the case, and then check if
`++i == fmt.size()`. That would increment i to `fmt.size() + 1`,
and so execution continues.
The intention is to move i beyond the ':', so we do it only in that
case instead.
2023-08-11 04:46:52 +02:00
Charlotte
51d9b73107
fmt: tests completing again
...
We need to invoke "read_verilog" manually, since the default action on
input files is to defer processing. Under such conditions, we never
simplify the AST, and initial $prints never execute.
2023-08-11 04:46:52 +02:00
Charlotte
9db73aa872
celltypes: add $print
...
Otherwise, the \TRG connection is pruned by CleanZeroWidthPass.
2023-08-11 04:46:52 +02:00
Charlotte
1eff84cb92
fmt: ensure test exits on fail
...
shebang not honoured when directly called with "bash run-test.sh".
2023-08-11 04:46:52 +02:00
whitequark
c285880684
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
whitequark
67052f62ec
fmt: add tests for Yosys evaluation of format expressions.
2023-08-11 04:46:52 +02:00
whitequark
3f8eab15bb
write_verilog: translate $print cells to $write tasks in always blocks.
2023-08-11 04:46:52 +02:00
whitequark
d51ecde8c2
clean: keep $print cells, since they have unmodelled side effects.
2023-08-11 04:46:52 +02:00
whitequark
d5c9953c09
ast: translate $display/$write tasks in always blocks to new $print cell.
2023-08-11 04:46:52 +02:00
whitequark
9f8e039a4b
ast: use new format string helpers.
2023-08-11 04:46:52 +02:00
whitequark
9ea241711e
kernel: add format string helpers, fmt.
2023-08-11 04:46:52 +02:00
whitequark
f8e2c955fc
read_verilog: set location of AST_TCALL.
...
Useful for error reporting of $display() arguments, etc.
2023-08-11 04:46:52 +02:00
Krystine Sherwin
685da6a2e5
Converting a number of inline commands to refs
...
Also reflowing text for line width.
Maybe look into supporting commands with options?
2023-08-08 12:45:47 +12:00
Krystine Sherwin
f8333e52f7
cmd links use title text
2023-08-08 12:19:13 +12:00
github-actions[bot]
389b8d0f94
Bump version
2023-08-08 00:16:52 +00:00
Krystine Sherwin
9fcf353734
Makefile adjustments to match top make
...
Hopefully matches enough that any `make docs` call will work from the yosys being built, while still being overridable locally.
2023-08-08 11:53:36 +12:00
Krystine Sherwin
8203a01ba9
Adding custom domain for cmdref
2023-08-08 11:51:57 +12:00
Krystine Sherwin
d8b8880ad6
Convert todo comments to directives
...
Could be left in for final version, but my current thinking is not?
2023-08-08 10:06:19 +12:00
Krystine Sherwin
ce9e56db47
Move the last presentation slides
2023-08-08 09:50:36 +12:00
Miodrag Milanovic
105c447010
Next dev cycle
2023-08-07 08:25:37 +02:00
Miodrag Milanovic
fbab08acf1
Release version 0.32
2023-08-07 08:22:52 +02:00
Krystine Sherwin
afc25afaf9
Minor tidying
2023-08-07 12:58:52 +12:00
Krystine Sherwin
8ade2182b0
Move (most of) ExOth and ExAdv slides
2023-08-07 12:58:40 +12:00
Krystine Sherwin
7ab051778e
Add copypaste reminder for typical_phases.rst
2023-08-07 10:40:36 +12:00
github-actions[bot]
e0ba07aed3
Bump version
2023-08-05 00:16:43 +00:00
Martin Povišer
ff3c7873f5
wreduce: Group reconnections
...
Group the reconnections, so that instead of producing
connect $auto$wreduce.cc:455:run$24 [0] 1'0
connect $auto$wreduce.cc:455:run$23 [31] 1'0
connect $auto$wreduce.cc:455:run$23 [30] 1'0
... (40 more lines)
we produce
connect $auto$wreduce.cc:461:run$23 [31:11] 21'000000000000000000000
connect $auto$wreduce.cc:461:run$24 [31:10] 22'0000000000000000000000
.
2023-08-04 14:43:59 +01:00
Miodrag Milanović
701b767736
Merge pull request #3871 from jix/smtbmc-sexpr-scan
...
smtbmc: Avoid quadratic behavior when scanning s-exprs
2023-08-04 14:47:50 +02:00
Krystine Sherwin
330a2272da
Converting PRESENTATION_ExSyn
2023-08-04 10:29:14 +12:00
Krystine Sherwin
4b40372446
Tidy/reflow some things
2023-08-03 10:37:43 +12:00
