mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 09:34:09 +00:00
Code Activity

Minor tidying

Browse source
This commit is contained in:
Krystine Sherwin 2023-08-07 12:58:52 +12:00
parent 8ade2182b0
commit afc25afaf9
No known key found for this signature in database
2 changed files with 4 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
docs/source/appendix/APPNOTE_011_Design_Investigation.rst
View file

@ -276,7 +276,7 @@ Interactive navigation
$procmux$5
.. code-block:: RTLIL
:caption: Output of ``dump \$2`` using the design from :numref:`example_src`
:caption: Output of ``dump $2`` using the design from :numref:`example_src`
and :numref:`example_out`
:name: dump2
@ -474,7 +474,7 @@ has no effect anymore.
:class: width-helper
:name: select_prod
Objects selected by ``select prod \%ci...``
Objects selected by ``select prod %ci...``
In most cases there are certain cell types and/or ports that should not be
considered for the ``%ci`` action, or we only want to follow certain cell types
@ -541,7 +541,7 @@ Or we could decide to tell the ``%ci`` action to not follow the ``CLK`` input:
:class: width-helper
:name: memdemo_01
Output of ``show y \%ci2:+\$dff[Q,D] \%ci*:-\$mux[S]:-\$dff``
Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff``
Next we would investigate the next logic level by adding another ``%ci2`` to
the command:

2
docs/source/getting_started/typical_phases.rst
View file

@ -1,4 +1,4 @@
Typical Phases of a Synthesis Flow
Typical phases of a synthesis flow
----------------------------------
.. TODO: copypaste