Akash Levy
e241c9d513
Merge branch 'YosysHQ:main' into main
2025-04-10 14:28:10 -07:00
Krystine Sherwin
cd3b914132
Reinstate #4768
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Revert the reversion so that we can fix the bugs that the PR missed.
2025-04-08 11:58:05 +12:00
Akash Levy
06c614a010
Merge branch 'YosysHQ:main' into main
2025-04-07 07:28:06 -07:00
Miodrag Milanović
d49364d96f
Revert "Refactor full_selection"
2025-04-07 12:11:55 +02:00
Akash Levy
0dab4308a3
Actual merge here
2025-04-06 18:53:43 -07:00
KrystalDelusion
98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections
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Refactor full_selection
2025-04-05 14:15:27 +13:00
Akash Levy
f218b5ba58
Revert "Represent memory size with size_t"
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This reverts commit bb5f8415af
2025-04-04 03:20:07 -07:00
Akash Levy
bb5f8415af
Represent memory size with size_t
2025-04-04 02:04:34 -07:00
Akash Levy
3d13f7aae2
Bump to latest
2025-03-26 14:56:10 -07:00
Emil J
ea74ad33a5
Merge pull request #4961 from YosysHQ/emil/cutpoint-typo
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cutpoint: fix typo
2025-03-25 21:30:29 +01:00
Emil J. Tywoniak
4991ed9d4b
cutpoint: fix typo
2025-03-25 18:10:47 +01:00
Akash Levy
95f489beec
Merge nice gzip refactor
2025-03-20 16:47:12 -07:00
Emil J. Tywoniak
4f3fdc8457
io: refactor string and file work into new unit
2025-03-19 13:43:42 +01:00
Krystine Sherwin
a3968d43f0
Drop deprecation on Design::selected_modules()
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Instead, change the default `Design::selected_modules()` to match the behaviour (i.e. `selected_unboxed_modules_warn()`) because it's a lot of files to touch and they don't really _need_ to be updated.
Also change `Design::selected_whole_modules()` users over to `Design::selected_unboxed_whole_modules()`, except `attrmap` because I'm not convinced it should be ignoring boxes. So instead, leave the deprecation warning for that one use and come back to the pass another time.
2025-03-14 14:08:56 +13:00
Krystine Sherwin
dac2bb7d4d
Use selection helpers
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Catch more uses of selection constructor without assigning a design.
2025-03-14 14:08:13 +13:00
Akash Levy
57bf3a6f51
Merge branch 'YosysHQ:main' into main
2025-01-14 08:38:59 -08:00
Emil J. Tywoniak
a58481e9b7
mark all hash_into methods nodiscard
2025-01-14 12:39:15 +01:00
Akash Levy
1dcf75d175
Sync
2024-12-19 21:40:30 -08:00
Emil J. Tywoniak
b9b9515bb0
hashlib: hash_eat -> hash_into
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
4e29ec1854
hashlib: acc -> eat
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
d071489ab1
hashlib: redo interface for flexibility
2024-12-18 14:49:25 +01:00
Alain Dargelas
88ff296657
Activity info and rename cmd
2024-12-11 11:04:35 -08:00
Akash Levy
2c5811daa1
Fix warnings
2024-12-09 11:45:09 -08:00
Alain Dargelas
fe684f5fd2
Precision fix
2024-12-03 09:35:11 -08:00
Alain Dargelas
f65d98a00d
Simulation information for macro power
2024-12-02 20:15:53 -08:00
Akash Levy
ea76abdaee
Merge
2024-11-11 11:47:58 -08:00
Martin Povišer
1b1a6c4aed
Merge pull request #4525 from georgerennie/peepopt_clock_gate
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peepopt: Add formal opt to rewrite latches to ffs in clock gates
2024-11-11 14:49:09 +01:00
Alain Dargelas
5be70f436f
Added stdout flush and statistical info for debug
2024-11-05 10:21:26 -08:00
Alain Dargelas
44fedf8186
Code cleanup
2024-10-23 09:33:06 -07:00
Alain Dargelas
2c506bfc1b
Corrected activity and duty
2024-10-22 16:26:49 -07:00
Alain Dargelas
c2aa611e5d
Fix comments and add freq annotation in sim pass
2024-10-21 15:53:48 -07:00
Alain Dargelas
7e2c45b1e6
Large datastructures pass by ref in lambda capture
2024-10-17 19:48:10 -07:00
Alain Dargelas
a54f450eb9
Fix coredump when wire is nullptr
2024-10-17 13:43:41 -07:00
Alain Dargelas
f6d67ac21e
More comments
2024-10-17 09:33:08 -07:00
Alain Dargelas
389518a8f0
tab issue
2024-10-16 21:37:41 -07:00
Alain Dargelas
516a4be6f8
Correct tab
2024-10-16 21:17:03 -07:00
Alain Dargelas
3f7c392e1a
activity computation
2024-10-16 20:41:26 -07:00
Emil J. Tywoniak
785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
Emily Schmidt
bdb59ffc8e
add -fst-noinit flag to sim for not initializing the state from the fst file
2024-08-21 11:03:29 +01:00
George Rennie
236c69bed4
clk2fflogic: run peepopt -formalclk before processing design
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* this attempts to rewrite clock gating patterns into a form that is
less likely to introduce combinational loops with clk2fflogic
* can be disabled with -nopeepopt which is useful for testing
clk2fflogic
2024-08-07 10:14:04 +01:00
Miodrag Milanovic
6d98418f3d
Set ranges on exported wires in VCD and FST
2024-08-02 15:23:00 +02:00
Martin Povišer
e063b96104
synthprop: Reformat the help
2024-07-25 11:43:58 +02:00
Jannis Harder
2bd889a59a
formalff -setundef: Fix handling for has_srst FFs
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The `has_srst`` case was checking `sig_ce` instead of `sig_srst` due to
a copy and paste error.
This would crash when `has_ce` was false and could incorrectly determine
that an initial value is unused when `has_ce` and `has_srst` are both
set.
2024-04-15 11:53:30 +02:00
N. Engelhardt
d70113a909
Merge pull request #3972 from nakengelhardt/celledges_shift_ops
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celledges: support shift ops
2024-03-08 09:35:47 +01:00
Jannis Harder
bbdfcfdf30
clk2fflogic: Fix handling of $check cells
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Fixes a bug in the handling of the recently introduced $check cells.
Both $check and $print cells in clk2fflogic are handled by the same code
and the existing tests for that were only using $print cells. This
missed a bug where the additional A signal of $check cells that is not
present on $print cells was dropped due to a typo, rendering $check
cells non-functional.
Also updates the tests to explicitly cover both cell types such that
they would have detected the now fixed bug.
2024-02-14 11:42:27 +01:00
Jannis Harder
e1a59ba80b
async2sync, clk2fflogic: Add support for $check and $print cells
2024-02-01 20:10:39 +01:00
Jannis Harder
7c818d30f7
sim: Bring $print trigger/sampling semantics in line with FFs
2024-01-25 16:21:03 +01:00
Martin Povišer
149bcd88ad
Merge pull request #4026 from uis246/fix-format
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Fix printf formats
2024-01-15 16:04:11 +01:00
uis
5902b2826d
Fix printf formats
2024-01-15 12:07:54 +01:00
Dag Lem
acf916f654
Restore sim output from initial $display
2024-01-14 16:52:51 +01:00
