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Author SHA1 Message Date
Eddie Hung
7f8c420cf7
Merge pull request #1166 from YosysHQ/eddie/synth_keepdc 
Add "synth -keepdc" option
 2019-07-08 21:43:16 -07:00
Eddie Hung
7600ffe4bd Merge branch 'master' of github.com:YosysHQ/yosys 2019-07-08 19:26:43 -07:00
Eddie Hung
7f964859ec synth_xilinx to call "synth -run coarse" with "-keepdc" 2019-07-08 19:23:24 -07:00
Eddie Hung
9ac078be6f Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7mux 2019-07-08 19:21:53 -07:00
Eddie Hung
41d7d9d24b Clarify script -scriptwire doc 2019-07-08 19:21:21 -07:00
Eddie Hung
fccabd0943 Add synth -keepdc to CHANGELOG 2019-07-08 19:15:37 -07:00
Eddie Hung
37b58f4324 Clarify 'wreduce -keepdc' doc 2019-07-08 19:15:07 -07:00
Eddie Hung
dd9771cbcd Add synth -keepdc option 2019-07-08 19:14:54 -07:00
Eddie Hung
3f86407cc3 Map $__XILINX_SHIFTX in a more balanced manner 2019-07-08 17:06:35 -07:00
Eddie Hung
78914e2e0e Capitalisation 2019-07-08 17:06:22 -07:00
Eddie Hung
baf47e496f Add synth_xilinx -widemux recommended value 2019-07-08 17:04:39 -07:00
Eddie Hung
ede1ef61c5
Merge pull request #1164 from YosysHQ/eddie/muxcover_mux2 
Add muxcover -mux2=cost option
 2019-07-08 14:34:37 -07:00
David Shah
22334fea40
Merge pull request #1160 from ZirconiumX/cyclone_v 
synth_intel: Warn about untested Quartus backend
 2019-07-08 21:04:33 +01:00
Eddie Hung
b5072256f2 Update muxcover doc as per @ZirconiumX 2019-07-08 12:50:59 -07:00
Eddie Hung
895ca50173 Fixes for 2:1 muxes 2019-07-08 12:03:38 -07:00
Eddie Hung
0944acf3af synth_xilinx -widemux=2 is minimum now 2019-07-08 11:29:21 -07:00
Eddie Hung
dbe1326573 Parametric muxcover costs as per @daveshah1 2019-07-08 11:08:20 -07:00
Eddie Hung
eb19abbb44 Merge remote-tracking branch 'origin/eddie/muxcover_mux2' into xc7mux 2019-07-08 11:00:31 -07:00
Eddie Hung
3681162c8d atoi -> stoi 2019-07-08 11:00:06 -07:00
Eddie Hung
a34c5612e7 Add muxcover -mux2=cost option 2019-07-08 10:59:12 -07:00
Eddie Hung
c58998a7d2 atoi -> stoi as per @daveshah1 2019-07-08 10:48:10 -07:00
Eddie Hung
c71ad5482e Merge remote-tracking branch 'origin/master' into xc7mux 2019-07-08 10:46:08 -07:00
whitequark
628437b01c verilog_backend: dump attributes on SwitchRule. 
This appears to be an omission.
 2019-07-08 15:11:29 +00:00
whitequark
48655dfb8b proc_mux: consider \src attribute on CaseRule. 2019-07-08 13:18:18 +00:00
whitequark
55c1f40277 verilog_backend: dump attributes on CaseRule, as comments. 
Attributes are not permitted in that position by Verilog grammar.
 2019-07-08 12:48:50 +00:00
whitequark
b1f400aeb8 genrtlil: emit \src attribute on CaseRule. 2019-07-08 12:29:08 +00:00
whitequark
93bc5affd3 Allow attributes on individual switch cases in RTLIL. 
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
 2019-07-08 11:34:58 +00:00
Dan Ravensloft
4f798cda9d synth_intel: Warn about untested Quartus backend 2019-07-07 19:26:31 +01:00
Clifford Wolf
030483ffb9
Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire 
Throw runtime exception when trying to convert inexistend C++ object to Python
 2019-07-05 11:57:41 +02:00
Benedikt Tutzer
3a1a41bdb1 Throw runtime exception when trying to convert a c++-pointer to a 
python-object in case the pointer is a nullptr to avoid a segfault.

Fixes #1090
 2019-07-04 14:20:13 +02:00
Eddie Hung
de26328130
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell 
write_xaiger to treat unknown cell connections as keep-s
 2019-07-03 09:43:00 -07:00
Clifford Wolf
e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144 
Improve specify dummy parser
 2019-07-03 12:30:37 +02:00
Clifford Wolf
1f173210eb Fix tests/various/specify.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-03 11:25:05 +02:00
Clifford Wolf
ba36567908 Some cleanups in "ignore specify parser" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-03 11:22:10 +02:00
Clifford Wolf
224ad8fe33
Merge pull request #1154 from whitequark/manual-sync-always 
manual: explain the purpose of `sync always`
 2019-07-03 10:45:29 +02:00
Eddie Hung
10524064e9 write_xaiger to treat unknown cell connections as keep-s 2019-07-02 19:14:30 -07:00
Eddie Hung
9c556e3c02 Add test 2019-07-02 19:13:40 -07:00
Eddie Hung
c35023d0bf Merge remote-tracking branch 'origin/master' into xc7mux 2019-07-02 10:21:10 -07:00
Eddie Hung
8455d1f4ff
Merge pull request #1150 from YosysHQ/eddie/script_from_wire 
Add "script -select [selection]" to allow commands to be taken from wires
 2019-07-02 10:20:42 -07:00
whitequark
9251c000e8 manual: explain the purpose of sync always. 2019-07-02 17:10:13 +00:00
Eddie Hung
43069e9eb9 Checkout yosys-0.9-rc branch of yosys-tests 2019-07-02 10:06:56 -07:00
Eddie Hung
810f8c5dbd Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup 2019-07-02 09:21:02 -07:00
Eddie Hung
879ae9d553 Merge remote-tracking branch 'origin/eddie/script_from_wire' into xc7mux 2019-07-02 09:04:50 -07:00
David Shah
0447794c51
Merge pull request #1153 from YosysHQ/dave/fix_multi_mux 
memory_dff: Fix checking of feedback mux input when more than one mux
 2019-07-02 16:47:54 +01:00
Eddie Hung
81a717e9b7 Update test for Pass::call_on_module() 2019-07-02 08:22:31 -07:00
Eddie Hung
f1504696e5 Use Pass::call_on_module() as per @cliffordwolf comments 2019-07-02 08:20:37 -07:00
Eddie Hung
90382a0f6d Update test too 2019-07-02 08:19:23 -07:00
Eddie Hung
02ba85b133 script -select -> script -scriptwire 2019-07-02 08:17:26 -07:00
David Shah
d45936fe5f memory_dff: Fix checking of feedback mux input when more than one mux 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-02 13:35:50 +01:00
Clifford Wolf
d206eca03b Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-02 11:36:26 +02:00