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	Merge remote-tracking branch 'origin/eddie/script_from_wire' into xc7mux
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						879ae9d553
					
				
					 3 changed files with 13 additions and 10 deletions
				
			
		|  | @ -12,7 +12,7 @@ Yosys 0.9 .. Yosys 0.9-dev | |||
|     - Added "synth_xilinx -abc9" (experimental) | ||||
|     - Added "synth_ice40 -abc9" (experimental) | ||||
|     - Added "synth -abc9" (experimental) | ||||
|     - Added "script -select" | ||||
|     - Added "script -scriptwire | ||||
|     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable) | ||||
| 
 | ||||
| 
 | ||||
|  |  | |||
|  | @ -1259,7 +1259,7 @@ struct ScriptCmdPass : public Pass { | |||
| 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 | ||||
| 		log("\n"); | ||||
| 		log("    script <filename> [<from_label>:<to_label>]\n"); | ||||
| 		log("    script -select [selection]\n"); | ||||
| 		log("    script -scriptwire [selection]\n"); | ||||
| 		log("\n"); | ||||
| 		log("This command executes the yosys commands in the specified file (default\n"); | ||||
| 		log("behaviour), or commands embedded in the constant text value connected to the\n"); | ||||
|  | @ -1276,17 +1276,17 @@ struct ScriptCmdPass : public Pass { | |||
| 	} | ||||
| 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE | ||||
| 	{ | ||||
| 		bool select_mode = false; | ||||
| 		bool scriptwire = false; | ||||
| 
 | ||||
| 		size_t argidx; | ||||
| 		for (argidx = 1; argidx < args.size(); argidx++) { | ||||
| 			if (args[argidx] == "-select") { | ||||
| 				select_mode = true; | ||||
| 			if (args[argidx] == "-scriptwire") { | ||||
| 				scriptwire = true; | ||||
| 				continue; | ||||
| 			} | ||||
| 			break; | ||||
| 		} | ||||
| 		if (select_mode) { | ||||
| 		if (scriptwire) { | ||||
| 			extra_args(args, argidx, design); | ||||
| 
 | ||||
| 			for (auto mod : design->selected_modules()) | ||||
|  | @ -1299,7 +1299,7 @@ struct ScriptCmdPass : public Pass { | |||
| 					if (!c.second.is_fully_const()) | ||||
| 						log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w)); | ||||
| 					auto v = c.second.as_const(); | ||||
| 					Pass::call(design, v.decode_string()); | ||||
| 					Pass::call_on_module(design, mod, v.decode_string()); | ||||
| 				} | ||||
| 		} | ||||
| 		else if (args.size() < 2) | ||||
|  |  | |||
|  | @ -6,12 +6,15 @@ read_verilog -formal <<EOT | |||
| 
 | ||||
|         wire [1023:0] _RUNME0 = "select -assert-count 2 t:foo"; | ||||
|         wire [1023:0] _RUNME1 = "select -assert-count 1 t:winnie"; | ||||
|         wire [1023:0] _DELETE = "delete c:bar"; | ||||
|     endmodule | ||||
| 
 | ||||
|     module other; | ||||
|         wire [1023:0] _DELETE = "cd; delete c:bar"; | ||||
|     endmodule | ||||
| EOT | ||||
| 
 | ||||
| script -select w:_RUNME* | ||||
| script -scriptwire w:_RUNME* | ||||
| 
 | ||||
| select w:_DELETE | ||||
| script -select | ||||
| script -scriptwire | ||||
| select -assert-count 1 t:foo | ||||
|  |  | |||
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