Emil J. Tywoniak
8333a83cef
opt_dff: more explicit testing, typo
2025-08-27 11:29:57 +02:00
Anhijkt
e1276560cd
opt_dff: add another test
2025-08-19 23:48:45 +03:00
Anhijkt
e486994f60
opt_dff: add test
2025-08-14 00:13:23 +03:00
Robert O'Callahan
8b75c06141
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
Martin Povišer
22a44e4333
Start opt_hier
2025-07-05 16:45:52 +02:00
George Rennie
7160c91800
tests: add test for #5164 opt_dff -sat UAF
2025-06-06 23:46:23 +01:00
George Rennie
353fd0f7f4
tests: test opt_expr for 32 bit unsigned shifts
2025-05-26 15:28:44 +01:00
George Rennie
d59380b3a0
tests: more complete testing of shift edgecases
2025-05-08 11:09:01 +02:00
George Rennie
af933b4f38
tests: check shifts by amounts that overflow int
2025-05-07 15:12:33 +02:00
George Rennie
70a44f035c
tests: test opt_expr constant shift edge cases
2025-04-26 12:40:04 +02:00
Krystine Sherwin
406b400458
opt_expr: Fix #4590
...
If all the (non-select) inputs of a `$_MUX{4,8,16}_` are undefined, replace it, just like we do for `$mux` and `$_MUX_`.
Add `tests/opt/opt_expr_mux_undef.ys` to verify this.
This doesn't do any const folding on the wide muxes, or shrinking to less wide muxes. It only handles the case where all inputs are 'x and the mux can be completely removed.
2025-04-04 12:25:31 +13:00
George Rennie
63b3ce0c77
Merge pull request #4971 from Anhijkt/pow-optimization
...
opt_expr: optimize pow of 2 cells
2025-04-03 14:34:36 +02:00
Anhijkt
c57cbfa8f9
opt_expr: add test
2025-04-01 21:54:46 +03:00
Emil J
3a1255546a
Merge pull request #4975 from YosysHQ/emil/opt_expr-cover-with-tests
...
opt_expr: expand test coverage
2025-03-31 20:13:16 +02:00
Emil J. Tywoniak
6194eb939d
opt_expr: expand test coverage
2025-03-31 19:31:53 +02:00
Emil J. Tywoniak
33bfc9d19c
opt_merge: test more kinds of cells
2025-03-10 13:14:06 +01:00
Emil J. Tywoniak
ae7a97cc2d
opt_merge: test some unary cells
2025-03-10 13:14:06 +01:00
Emil J. Tywoniak
176faae7c9
opt_merge: fix trivial binary regression
2025-03-10 13:14:06 +01:00
Krystine Sherwin
db5b76edc1
Add test for shifting by INT_MAX
...
Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.
2025-02-14 14:01:27 +13:00
Emil J. Tywoniak
6240aec433
test: restore verific handling, nicer naming
2024-12-13 10:24:47 +01:00
George Rennie
9043dc0ad6
tests: replace read_ilang with read_rtlil
...
* #4612 was written before read_ilang was deprecated but merged after so caused test failures. This switches read_ilang to read_rtlil
2024-11-20 14:54:23 +01:00
Emil J
cc17d5bb70
Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width
...
opt_demorgan: skip zero width cells
2024-11-20 13:33:16 +01:00
Emil J
18459b4b09
Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width
...
opt_reduce: keep at least one input to $reduce_or/and cells
2024-11-20 13:33:04 +01:00
Krystine Sherwin
ee73a91f44
Remove references to ilang
2024-11-05 12:36:31 +13:00
George Rennie
0572f8806f
opt_reduce: add test for constant $reduce_and/or not being zero width
2024-09-25 16:28:41 +01:00
George Rennie
e105cae4a9
opt_demorgan: add test for zero width cell
2024-09-25 16:10:16 +01:00
phsauter
34b5c6d062
peepopt: avoid shift-amount underflow
2024-06-13 23:30:07 +02:00
Martin Povišer
5924d97381
tests: Remove part of test involving combinational loops
2024-03-11 10:45:36 +01:00
Charlotte
d130f7fca2
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00
Martin Povišer
f8325f66b7
opt_expr: Fix 'signed X>=0' replacement for wide output ports
...
If the `$ge` cell we are replacing has wide output port, the upper bits
on the port should be driven to zero. That's not what a `$not` cell with
a single-bit input does. Instead opt for a `$logic_not` cell, which does
zero-pad its output.
Fixes #3867 .
2023-08-01 13:50:12 +01:00
Martin Povišer
f0ae046c5a
opt_share: Fix input confusion with ANDNOT, ORNOT gates
...
Distinguish between the A, B input ports of `$_ANDNOT_`, `$_ORNOT_`
gates when considering those for sharing. Unlike the input ports of the
other supported single-bit gates, those are not interchangeable.
Fixes #3848 .
2023-07-20 20:58:52 +01:00
Jannis Harder
661fa5ff92
simplemap: Map $xnor to $_XNOR_ cells
...
The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of
the `$_XNOR_` cell.
2022-11-29 19:06:45 +01:00
Jannis Harder
0113f44faa
Reenable existing equiv_opt tests
2022-10-07 16:04:51 +02:00
Jannis Harder
81906aa627
Fix tests for check in equiv_opt
2022-10-07 16:04:51 +02:00
Claire Xenia Wolf
f0478c520d
Re-enable opt_dff_sr equiv_opt checks
...
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-10-07 16:04:51 +02:00
Marcelina Kościelnicka
606f1637ae
Add memory_bmux2rom pass.
2022-05-18 22:48:55 +02:00
Jannis Harder
ca5b910296
opt_merge: Add -keepdc option required for formal verification
...
The `-keepdc` option prevents merging flipflops with dont-care bits in
their initial value, as, in general, this is not a valid transform for
formal verification.
The keepdc option of `opt` is passed along to `opt_merge` now.
2022-04-01 21:03:20 +02:00
Marcelina Kościelnicka
07a657fb0c
opt_reduce: Add $bmux and $demux optimization patterns.
2022-01-30 03:37:52 +01:00
Marcelina Kościelnicka
f84c9d8e17
memory_share: Fix SAT-based sharing for wide ports.
...
Fixes #3117 .
2021-12-20 18:40:14 +01:00
Marcelina Kościelnicka
e64456f920
extract_reduce: Refactor and fix input signal construction.
...
Fixes #3047 .
2021-10-21 04:10:01 +02:00
Marcelina Kościelnicka
1f74ec3535
memory_share: Add -nosat and -nowiden options.
...
This unlocks wide port recognition by default.
2021-08-14 00:09:04 +02:00
Marcelina Kościelnicka
9fdedf4d1c
memory_dff: Recognize soft transparency logic.
2021-08-13 23:08:32 +02:00
Marcelina Kościelnicka
616ace2d92
Add new opt_mem_priority pass.
2021-08-13 11:58:52 +02:00
Marcelina Kościelnicka
24027b5446
proc_memwr: Use the v2 memwr cell.
2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka
fd79217763
Add v2 memory cells.
2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka
98003430d6
opt_merge: Use FfInitVals.
...
Partial #2920 fix.
2021-08-08 01:19:22 +02:00
Marcelina Kościelnicka
8bdc019730
verilog: Emit $meminit_v2 cell.
...
Fixes #2447 .
2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka
436d42c00c
opt_expr: Propagate constants to port connections.
...
This adds one simple piece of functionality to opt_expr: when a cell
port is connected to a fully-constant signal (as determined by sigmap),
the port is reconnected directly to the constant value. This is just
enough optimization to fix the "non-constant $meminit input" problem
without requiring a full opt_clean or a separate pass.
2021-07-27 20:44:26 +02:00
Marcelina Kościelnicka
438bcc68c0
Add regression test for #2824 .
2021-06-11 12:06:35 +01:00
Marcelina Kościelnicka
13b901bf1c
memory_map: Improve start_offset handling.
...
Fixes #2775 .
2021-05-31 17:45:21 +02:00
