Eddie Hung
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b1f1db2fcf
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Fixes
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2019-04-11 16:17:09 -07:00 |
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Eddie Hung
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e8c26f2839
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WIP
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2019-04-11 15:52:04 -07:00 |
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Eddie Hung
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09e7eb7aed
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Spelling fixes
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2019-04-11 15:09:13 -07:00 |
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Eddie Hung
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7685469ee2
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Add default entry to testcase
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2019-04-11 15:03:40 -07:00 |
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Eddie Hung
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adc6efb584
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Recognise default entry in case even if all cases covered (#931)
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2019-04-11 12:34:51 -07:00 |
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Eddie Hung
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0deaccbaae
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Fix a few typos
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2019-04-08 16:46:33 -07:00 |
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Clifford Wolf
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e194e65358
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Merge pull request #919 from YosysHQ/multiport_transp
memory_bram: Fix multiport make_transp
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2019-04-08 21:14:05 +02:00 |
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David Shah
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2bf3ca6443
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memory_bram: Fix multiport make_transp
Signed-off-by: David Shah <dave@ds0.me>
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2019-04-07 16:56:31 +01:00 |
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Clifford Wolf
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dfb242c905
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Add "read_ilang -lib"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-05 17:31:49 +02:00 |
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Clifford Wolf
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75ca06526a
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Added missing argument checking to "mutate" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-04 18:10:10 +02:00 |
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Eddie Hung
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ef84b434a5
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Merge pull request #913 from smunaut/fix_proc_mux
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
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2019-04-03 06:27:41 -07:00 |
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Sylvain Munaut
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39380c45ba
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proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
last_mux_cell can be NULL ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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2019-04-03 14:50:12 +02:00 |
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Clifford Wolf
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721fa1cbd8
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Merge pull request #912 from YosysHQ/bram_addr_en
memory_bram: Consider read enable for address expansion register
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2019-04-03 10:00:18 +02:00 |
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Clifford Wolf
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3f6554d698
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Merge pull request #910 from ucb-bar/memupdates
Refine memory support to deal with general Verilog memory definitions.
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2019-04-03 09:59:11 +02:00 |
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David Shah
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6acbc016f4
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memory_bram: Consider read enable for address expansion register
Signed-off-by: David Shah <dave@ds0.me>
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2019-04-02 19:47:50 +01:00 |
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Eddie Hung
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aaa2690a56
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Merge pull request #895 from YosysHQ/pmux2shiftx
RFC: Add a pmux-to-shiftx optimisation to proc_mux
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2019-04-02 00:16:14 -07:00 |
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Jim Lawson
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73b87e7807
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Refine memory support to deal with general Verilog memory definitions.
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2019-04-01 15:02:12 -07:00 |
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Clifford Wolf
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22035c20ff
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Merge pull request #907 from YosysHQ/clifford/fix906
Build Verilog parser with -DYYMAXDEPTH=100000
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2019-03-30 00:09:42 +01:00 |
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Clifford Wolf
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584d2030bf
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Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-29 16:32:44 +01:00 |
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Clifford Wolf
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32bd0f22ec
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Merge pull request #901 from trcwm/libertyfixes
Libertyfixes: accept superfluous ; at end of group.
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2019-03-28 09:32:05 +01:00 |
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Clifford Wolf
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662429cc49
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Merge pull request #903 from YosysHQ/bram_reset_transp
memory_bram: Reset make_transp when growing read ports
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2019-03-28 09:30:48 +01:00 |
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David Shah
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60594ad40c
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memory_bram: Reset make_transp when growing read ports
Signed-off-by: David Shah <dave@ds0.me>
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2019-03-27 17:19:14 +00:00 |
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Niels Moseley
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263ab60b43
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Liberty file parser now accepts superfluous ;
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2019-03-27 15:17:58 +01:00 |
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Niels Moseley
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ee130f67cd
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Liberty file parser now accepts superfluous ;
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2019-03-27 15:16:19 +01:00 |
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Niels Moseley
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487cb45b87
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Liberty file parser now accepts superfluous ;
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2019-03-27 15:15:53 +01:00 |
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Clifford Wolf
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7682629b79
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Add "read -verific" and "read -noverific"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-27 14:03:35 +01:00 |
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Clifford Wolf
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2c7fe42ad1
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Add "rename -output"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-27 13:47:42 +01:00 |
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Clifford Wolf
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d351b7cb99
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Improve "rename" help message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-27 13:33:26 +01:00 |
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Clifford Wolf
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38b3fbd3f0
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Add "cutpoint -undef"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-26 16:01:14 +01:00 |
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Clifford Wolf
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d0b9b1bece
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Add "hdlname" attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-26 14:52:48 +01:00 |
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Clifford Wolf
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c863796e9f
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Fix "verific -extnets" for more complex situations
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-26 14:17:46 +01:00 |
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Clifford Wolf
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ddc1a4488e
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Add "cutpoint" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-25 19:49:00 +01:00 |
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Eddie Hung
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b7a3d35c6b
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Create one $shiftx per bit in width
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2019-03-25 11:16:56 -07:00 |
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Clifford Wolf
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9ec50ca7b9
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Merge pull request #896 from YosysHQ/transp_fixes
memory_bram: Fix multiclock make_transp
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2019-03-25 14:55:16 +01:00 |
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Clifford Wolf
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2bb9632944
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Merge pull request #897 from trcwm/libertyfixes
Liberty parser: Accept ranges [A:B], and ignore missing ';'.
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2019-03-25 14:47:33 +01:00 |
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Niels Moseley
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1f7f54e68e
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spaces -> tabs
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2019-03-25 14:12:04 +01:00 |
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Niels Moseley
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9d9cc8a314
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EOL is now accepted as ';' replacement on lines that look like: feature_xyz(option)
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2019-03-25 12:15:10 +01:00 |
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Niels Moseley
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3b3b77291a
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Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.
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2019-03-24 22:54:18 +01:00 |
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David Shah
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ac6cc88db3
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memory_bram: Fix multiclock make_transp
Signed-off-by: David Shah <dave@ds0.me>
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2019-03-24 16:21:36 +00:00 |
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Eddie Hung
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2507d01b03
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Add a pmux-to-shiftx optimisation to proc_mux
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2019-03-23 16:45:36 -07:00 |
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Clifford Wolf
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ccfa2fe01c
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Add "mutate -none -mode", "mutate -mode none"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-23 20:20:32 +01:00 |
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Clifford Wolf
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59c44bb61a
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Add "mutate -s <filename>"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-23 17:53:09 +01:00 |
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Clifford Wolf
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2cf71e2a7b
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Merge pull request #893 from YosysHQ/clifford/btormeminit
Memory init support in write_btor
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2019-03-23 16:02:01 +01:00 |
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Clifford Wolf
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1eff8be8f0
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Add support for memory initialization to write_btor
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-23 14:40:01 +01:00 |
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Clifford Wolf
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e78f5a3055
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Fix BTOR output tags syntax in writye_btor
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-23 14:39:42 +01:00 |
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Clifford Wolf
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3b796c033c
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Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-23 14:38:48 +01:00 |
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Clifford Wolf
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a440f82586
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Merge pull request #889 from YosysHQ/clifford/fix888
Fix mem2reg handling of memories with upto data ports
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2019-03-22 18:03:06 +01:00 |
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Clifford Wolf
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7d8d0d0155
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Merge pull request #890 from YosysHQ/clifford/fix887
Trim init attributes when resizing FFs in "wreduce"
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2019-03-22 18:02:29 +01:00 |
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David Shah
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7a6551de36
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Merge pull request #891 from YosysHQ/xilinx_keep
xilinx: Add keep attribute where appropriate
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2019-03-22 14:28:29 +00:00 |
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David Shah
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46f6a60d58
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xilinx: Add keep attribute where appropriate
Signed-off-by: David Shah <dave@ds0.me>
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2019-03-22 13:57:17 +00:00 |
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