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1992 commits

Author SHA1 Message Date
Marcelina Kościelnicka
ea79e16bab xilinx_dffopt: Don't crash on missing IS_*_INVERTED. 
The presence of IS_*_INVERTED on FD* cells follows Vivado, which
apparently has been decided by a dice roll.  Just assume false if the
parameter doesn't exist.

Fixes #2559.
 2021-01-27 00:32:00 +01:00
Marcelina Kościelnicka
cd6f0732f3 xilinx: Add FDRSE_1, FDCPE_1. 2021-01-27 00:32:00 +01:00
Tom Verbeure
87637e8359 Fix some trivial typos. 2021-01-03 23:52:59 -08:00
whitequark
b0d4c63957
Merge pull request #2480 from YosysHQ/dave/nexus-lram 
nexus: Add LRAM inference
 2021-01-01 09:49:00 +00:00
Marcelina Kościelnicka
f2932628fc xilinx: Add some missing blackbox cells. 2020-12-21 05:34:26 +01:00
Marcelina Kościelnicka
5ffb676fa9 xilinx: Regenerate cells_xtra.v using Vivado 2020.2 2020-12-21 05:34:26 +01:00
Marcelina Kościelnicka
871fc34ad4 xilinx: Add FDDRCPE and FDDRRSE blackbox cells. 
These are necessary primitives for proper DDR support on Virtex 2 and
Spartan 3.
 2020-12-17 03:25:07 +01:00
David Shah
17812a1560 nexus: Add LRAM inference 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-07 13:27:17 +00:00
David Shah
264e924abb nexus: More efficient CO mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 17:08:39 +00:00
Pepijn de Vos
f155826a70 add -noalu and -json option for apicula 2020-11-30 11:43:12 +01:00
David Shah
9f241c9a42 nexus: DSP inference support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-20 08:45:55 +00:00
Miodrag Milanović
c8d809897f
Merge pull request #2441 from YosysHQ/dave/nexus_dsp_sim 
nexus: Add DSP simulation model
 2020-11-18 12:22:05 +01:00
David Shah
923843b3fa nexus: Add DSP simulation model 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-18 10:21:17 +00:00
Miodrag Milanovic
aa4d94f7d8 Fix duplicated parameter name typo 2020-11-18 10:03:57 +01:00
Konrad Beckmann
5b9a975eba synth_gowin: Add rPLL blackbox 2020-11-11 17:06:54 +01:00
David Shah
6d63e58e46 nexus: Add make_transp to BRAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-22 15:11:59 +01:00
clairexen
e919d0c125
Merge pull request #2405 from byuccl/fix_xilinx_cells 
xilinx/cells_sim.v: Move signal declaration to before first use
 2020-10-20 17:11:36 +02:00
Jeff Goeders
8be56960a2 Move signal declarations to before first use 
Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
 2020-10-19 16:09:18 -06:00
David Shah
4d584d9319 synth_nexus: Initial implementation 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-15 08:52:15 +01:00
Eddie Hung
de79978372
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) 
* xilinx: eliminate SCCs from DSP48E1 model

* xilinx: add SCC test for DSP48E1

* Update techlibs/xilinx/cells_sim.v

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled
 2020-09-23 09:15:24 -07:00
Dan Ravensloft
028f96e536 intel_alm: better map wide but shallow multiplies 2020-08-28 23:44:16 +02:00
Dan Ravensloft
1a07b330f8 intel_alm: Add multiply signedness to cells 
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
 2020-08-26 22:50:16 +02:00
Marcelina Kościelnicka
082cbcb4c7 synth_intel: Remove incomplete Arria 10 GX support. 
The techmap rules for this target do not work in the first place (note
lack of >2-input LUT mappings), and if proper support is ever added,
it'd be better placed in the synth_intel_alm backend.
 2020-08-21 01:46:06 +02:00
Dan Ravensloft
034b9ec716 intel: move Cyclone V support to intel_alm 2020-08-20 18:25:05 +02:00
clairexen
d9dd8bc748
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes 
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
 2020-08-20 16:25:56 +02:00
clairexen
1cdb533fa5
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern 
techmap: Add support for [] wildcards in techmap_celltype.
 2020-08-20 16:18:40 +02:00
Marcelina Kościelnicka
50d532f01c techmap/shift_shiftx: Remove the "shiftx2mux" special path. 
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering.  This path was needlessly
overcomplicated and contained bugs.

Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling).  This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.

Fixes #2346.
 2020-08-20 12:44:09 +02:00
Xiretza
928fd40c2e Respect \A_SIGNED for $shift 
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
 2020-08-18 19:36:24 +02:00
Dan Ravensloft
3b534a203a intel_alm: fix typo in MISTRAL_MUL27X27 cell name 2020-08-13 17:08:50 +02:00
Dan Ravensloft
97daf612cb intel_alm: add more megafunctions. NFC. 2020-08-12 18:39:22 +02:00
Marcelina Kościelnicka
9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka
522788f016 techmap: Add support for [] wildcards in techmap_celltype. 
Fixes #1826.
 2020-08-02 22:46:48 +02:00
Marcelina Kościelnicka
6cd135a5eb opt_expr: Remove -clkinv option, make it the default. 
Adds -noclkinv option just in case the old behavior was actually useful
to someone.
 2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka
cf60699884 synth_ice40: Use opt_dff. 
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka
8501342fc5 synth_xilinx: Use opt_dff. 
The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:09 +02:00
Dan Ravensloft
a2fb84fd0c intel_alm: direct M10K instantiation 
This reverts commit a3a90f6377.
 2020-07-27 15:39:06 +02:00
Dan Ravensloft
62311b7ec0 intel_alm: increase abc9 -W 2020-07-26 23:56:54 +02:00
clairexen
02583ad504
Merge pull request #2294 from Ravenslofty/intel_alm_timings 
intel_alm: add additional ABC9 timings
 2020-07-23 18:21:20 +02:00
Dan Ravensloft
4d9d90079c intel_alm: add additional ABC9 timings 2020-07-23 11:57:07 +01:00
Keith Rothman
819f1d8c20 Remove EXPLICIT_CARRY logic. 
The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY
within yosys itself.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-07-23 00:56:09 +02:00
Marcelina Kościelnicka
1b95b0e570 sf2: Emit CLKINT even if -clkbuf not passed 
This restores pre #2229 behavior.
 2020-07-17 15:01:47 +02:00
Miodrag Milanović
10bc0967e2
Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix 
anlogic: Fix FF mapping.
 2020-07-17 14:39:31 +02:00
Marcelina Kościelnicka
a4f7777e9d anlogic: Fix FF mapping. 2020-07-17 14:03:21 +02:00
clairexen
9a5d6e1789
Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobs 
sf2: replace sf2_iobs with {clkbuf,iopad}map
 2020-07-16 18:33:56 +02:00
Miodrag Milanović
910f421324
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic 
anlogic: Use dfflegalize.
 2020-07-16 18:07:58 +02:00
Miodrag Milanović
b74eb598bc
Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbuf 
efinix: Nuke efinix_gbuf in favor of clkbufmap.
 2020-07-16 18:07:41 +02:00
Marcelina Kościelnicka
a786091b46 achronix: Use dfflegalize. 2020-07-14 23:12:16 +02:00
Marcelina Kościelnicka
3050454d6e anlogic: Use dfflegalize. 2020-07-14 05:02:50 +02:00
Marcelina Kościelnicka
3209c0762a intel: Use dfflegalize. 2020-07-13 19:21:05 +02:00
Lofty
a3a90f6377 Revert "intel_alm: direct M10K instantiation" 
This reverts commit 09ecb9b2cf.
 2020-07-13 18:05:38 +02:00