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synth_ice40: Use opt_dff.

Browse source 
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
This commit is contained in:
Marcelina Kościelnicka 2020-07-22 13:34:11 +02:00
parent 8501342fc5
commit cf60699884
7 changed files with 93 additions and 390 deletions
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1
techlibs/ice40/Makefile.inc
View file

@ -1,7 +1,6 @@
OBJS += techlibs/ice40/synth_ice40.o
OBJS += techlibs/ice40/ice40_braminit.o
OBJS += techlibs/ice40/ice40_ffssr.o
OBJS += techlibs/ice40/ice40_opt.o
GENFILES += techlibs/ice40/brams_init1.vh

131
techlibs/ice40/ice40_ffssr.cc
View file

@ -1,131 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct Ice40FfssrPass : public Pass {
Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { }
void help() override
{
log("\n");
log(" ice40_ffssr [options] [selection]\n");
log("\n");
log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
// if (args[argidx] == "-singleton") {
// singleton_mode = true;
// continue;
// }
break;
}
extra_args(args, argidx, design);
pool<IdString> sb_dff_types;
sb_dff_types.insert(ID(SB_DFF));
sb_dff_types.insert(ID(SB_DFFE));
sb_dff_types.insert(ID(SB_DFFN));
sb_dff_types.insert(ID(SB_DFFNE));
for (auto module : design->selected_modules())
{
log("Merging set/reset $_MUX_ cells into SB_FFs in %s.\n", log_id(module));
SigMap sigmap(module);
dict<SigBit, Cell*> sr_muxes;
vector<Cell*> ff_cells;
for (auto cell : module->selected_cells())
{
if (sb_dff_types.count(cell->type)) {
ff_cells.push_back(cell);
continue;
}
if (cell->type != ID($_MUX_))
continue;
SigBit bit_a = sigmap(cell->getPort(ID::A));
SigBit bit_b = sigmap(cell->getPort(ID::B));
if (bit_a.wire == nullptr || bit_b.wire == nullptr)
sr_muxes[sigmap(cell->getPort(ID::Y))] = cell;
}
for (auto cell : ff_cells)
{
if (cell->get_bool_attribute(ID(dont_touch)))
continue;
SigSpec sig_d = cell->getPort(ID::D);
if (GetSize(sig_d) < 1)
continue;
SigBit bit_d = sigmap(sig_d[0]);
if (sr_muxes.count(bit_d) == 0)
continue;
Cell *mux_cell = sr_muxes.at(bit_d);
SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
SigBit bit_s = sigmap(mux_cell->getPort(ID::S));
log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
SigBit sr_val, sr_sig;
if (bit_a.wire == nullptr) {
bit_d = bit_b;
sr_val = bit_a;
sr_sig = module->NotGate(NEW_ID, bit_s);
} else {
log_assert(bit_b.wire == nullptr);
bit_d = bit_a;
sr_val = bit_b;
sr_sig = bit_s;
}
if (sr_val == State::S1) {
cell->type = cell->type.str() + "SS";
cell->setPort(ID::S, sr_sig);
cell->setPort(ID::D, bit_d);
} else {
cell->type = cell->type.str() + "SR";
cell->setPort(ID::R, sr_sig);
cell->setPort(ID::D, bit_d);
}
}
}
}
} Ice40FfssrPass;
PRIVATE_NAMESPACE_END

4
techlibs/ice40/ice40_opt.cc
View file

@ -215,7 +215,7 @@ struct Ice40OptPass : public Pass {
log(" <ice40 specific optimizations>\n");
log(" opt_expr -mux_undef -undriven [-full]\n");
log(" opt_merge\n");
log(" opt_rmdff\n");
log(" opt_dff\n");
log(" opt_clean\n");
log(" while <changed design>\n");
log("\n");
@ -247,7 +247,7 @@ struct Ice40OptPass : public Pass {
Pass::call(design, "opt_expr " + opt_expr_args);
Pass::call(design, "opt_merge");
Pass::call(design, "opt_rmdff");
Pass::call(design, "opt_dff");
Pass::call(design, "opt_clean");
if (design->scratchpad_get_bool("opt.did_something") == false)

12
techlibs/ice40/synth_ice40.cc
View file

@ -293,6 +293,10 @@ struct SynthIce40Pass : public ScriptPass
run("opt_clean");
run("check");
run("opt");
run("fsm");
run("opt");
run("opt_dff");
run("opt");
run("wreduce");
run("peepopt");
run("opt_clean");
@ -316,8 +320,6 @@ struct SynthIce40Pass : public ScriptPass
}
run("alumacc");
run("opt");
run("fsm");
run("opt -fast");
run("memory -nomap");
run("opt_clean");
}
@ -354,11 +356,6 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("map_ffs"))
{
if (!nodffe)
run("dff2dffe -direct-match $_DFF_*");
if (min_ce_use >= 0) {
run("opt_merge");
}
if (nodffe)
run(stringf("dfflegalize -cell $_DFF_?_ 0 -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0 -cell $_DLATCH_?_ x"));
else
@ -366,7 +363,6 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/ice40/ff_map.v");
run("opt_expr -mux_undef");
run("simplemap");
run("ice40_ffssr");
run("ice40_opt -full");
}