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yosys/techlibs
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Dan Ravensloft 1a07b330f8 intel_alm: Add multiply signedness to cells 
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
2020-08-26 22:50:16 +02:00
..
achronix achronix: Use dfflegalize. 2020-07-14 23:12:16 +02:00
anlogic anlogic: Fix FF mapping. 2020-07-17 14:03:21 +02:00
common Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes 2020-08-20 16:25:56 +02:00
coolrunner2 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
easic Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
ecp5 Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
efinix techmap: Add support for [] wildcards in techmap_celltype. 2020-08-02 22:46:48 +02:00
gowin Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
greenpak4 opt_expr: Remove -clkinv option, make it the default. 2020-07-31 00:08:15 +02:00
ice40 Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
intel synth_intel: Remove incomplete Arria 10 GX support. 2020-08-21 01:46:06 +02:00
intel_alm intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
sf2 sf2: Emit CLKINT even if -clkbuf not passed 2020-07-17 15:01:47 +02:00
xilinx Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00