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Code Activity
13773 commits 95 branches 53 tags 45 MiB
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13773 commits

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Author SHA1 Message Date
Akash Levy
aec3df36d1 Make flatten less expressive 2024-07-07 21:46:23 -07:00
Akash Levy
39e8fc90bc Smallfix 2024-07-07 17:33:33 -07:00
Akash Levy
9fc7a31fe6 Smallfix 2024-07-07 15:47:57 -07:00
Akash Levy
75af87023e Smallfix 2024-07-07 15:36:04 -07:00
Akash Levy
f40d54736b Update Verific to June_2024 release 2024-07-07 15:21:10 -07:00
Akash Levy
c85b8a8a4d
Merge branch 'YosysHQ:main' into master 2024-07-06 15:12:11 -07:00
N. Engelhardt
dac5bd1983
Merge pull request #4455 from phsauter/shiftadd-limit-padding 
peepopt: limit padding from shiftadd
 2024-07-06 08:10:25 +02:00
Akash Levy
70016a08b8 Disable debug 2024-07-03 06:55:53 -07:00
Akash Levy
30241e07eb Fix segfault 2024-07-03 02:29:48 -07:00
Akash Levy
80b50f136d Debug on 2024-07-02 19:02:58 -07:00
Akash Levy
e22cded6d4 Fix 2024-07-02 17:36:41 -07:00
Akash Levy
fcd073ab51 Smallfix 2024-07-02 15:13:58 -07:00
Akash Levy
6204be060c Enable Verific 2024-07-02 15:13:03 -07:00
Akash Levy
0596766cbd Merge upstream yosys changes 2024-07-01 18:33:38 -07:00
Akash Levy
0b47da5969 Smallfix 2024-07-01 12:51:46 -07:00
Akash Levy
5def05a5dd Smallfix 2024-07-01 04:20:52 -07:00
Akash Levy
fe0c3b0ae1 Update verific 2024-07-01 03:38:59 -07:00
Akash Levy
fee4caafb7 Don't display on stdout in py_wrap_generator when using log_to_stream 2024-07-01 02:29:49 -07:00
github-actions[bot]
a739e21a5f Bump version 2024-06-29 00:16:56 +00:00
Catherine
580aaa362d
opt_lut_ins: fix name of global object. NFCI 2024-06-28 15:12:36 +00:00
Akash Levy
dec43679be See if this fixes issues on Innatera design 2024-06-28 03:13:38 -07:00
Martin Povišer
07daf61ae6
Merge pull request #4467 from povik/fix-add-shiftx 
rtlil: Fix `addShiftx` for signed shifts
 2024-06-26 18:17:28 +02:00
github-actions[bot]
1288166f7a Bump version 2024-06-25 00:17:11 +00:00
Miodrag Milanović
1e401c3e04
Merge pull request #4460 from YosysHQ/micko/c++17 
Make C++17 compiler required
 2024-06-24 19:54:30 +02:00
Miodrag Milanovic
777624ccf5 Make yosys-config dependant of Makefile 2024-06-24 16:08:08 +02:00
Martin Povišer
89d939334e rtlil: Fix addShiftx for signed shifts 
Only the `B` input (the shift amount) can be marked as signed on a
`$shiftx` cell. Adapt the helper accordingly and prevent it from
creating invalid RTLIL when called with `is_signed` set. Previously
it would mark both `A` and `B` as signed.
 2024-06-21 15:14:08 +02:00
github-actions[bot]
6c8ae44ae7 Bump version 2024-06-20 00:17:08 +00:00
gatecat
22d8df1e7e liberty: Support for IO liberty files for verification 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-06-19 21:12:42 +02:00
Akash Levy
6795c32167 Make scopeinfo not default 2024-06-19 04:05:02 -07:00
Akash Levy
e093ac5bca Update verific 2024-06-19 00:56:27 -07:00
github-actions[bot]
ede3750a6c Bump version 2024-06-19 00:17:13 +00:00
Miodrag Milanović
8024688b1d
Merge pull request #4459 from YosysHQ/micko/vanilla_verific 
Verific build support improvements
 2024-06-18 10:50:20 +02:00
Akash Levy
983d404e93 Smallfix 2024-06-17 20:04:38 -07:00
Akash Levy
c8dff00ca6 Smallfix 2024-06-17 16:07:26 -07:00
Akash Levy
719bbd7523 Improve SCC reporting 2024-06-17 14:18:41 -07:00
Miodrag Milanovic
2bbf3112d9 Update VS build to C++17 build 2024-06-17 17:29:20 +02:00
Martin Povišer
f9b7b8fff0 Update documentation for C++17 switch 2024-06-17 17:08:13 +02:00
Miodrag Milanovic
141a2e3638 Make C++17 compiler required 2024-06-17 16:55:36 +02:00
Miodrag Milanovic
dfde792288 Refactored import code 2024-06-17 14:49:58 +02:00
Miodrag Milanovic
19da7f7d59 Update makefile to make options uniform 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
0f3f731254 Handle -work for vhdl, and clean messages 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
0a81c8e161 Import all modules from all libraries when when needed 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
7c3094633d Compile with hier_tree separate SV and VHDL as well 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
e2e189647f Cleanup 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
7bec332b68 SV + VHDL with RTL support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
25d50bb2af VHDL only build support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
54bf9ccf06 Add initial support for Verific without additional YosysHQ patch 2024-06-17 13:29:11 +02:00
Akash Levy
a0c0384683 Preserve instances 2024-06-16 20:20:10 -07:00
Akash Levy
e23e33441f Update yosys from upstream 2024-06-15 14:23:24 -07:00
Akash Levy
fce46d2a53 Add better Yosys/Verific name aliasing and reenable dffe opt 2024-06-15 14:18:33 -07:00