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1701 commits

Author SHA1 Message Date
Eddie Hung
721f6a14fb read_aiger to accept empty string for clk_name, passable only if no latches 2019-02-25 15:34:02 -08:00
Eddie Hung
0ca3fd6a1c abc9 not to clean after aigmap 2019-02-25 15:31:52 -08:00
Eddie Hung
51f28a6747 abc9 to call "clean" once at the end of all abc9_module() calls 2019-02-25 12:55:47 -08:00
Clifford Wolf
c258b99040 Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:41:36 +01:00
Clifford Wolf
c118f9a377
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
Define basic_cell_type() function and use it to derive the cell type …
2019-02-24 11:39:13 -08:00
Clifford Wolf
cd722f26a5 Cleanups in ARST handling in wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:34:23 +01:00
Clifford Wolf
da14bc8524
Merge pull request #824 from litghost/fix_reduce_on_ff
Fix WREDUCE on FF not fixing ARST_VALUE parameter.
2019-02-24 11:29:14 -08:00
Jim Lawson
71bcc4c644 Address requested changes - don't require non-$ name.
Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
2019-02-22 16:06:10 -08:00
Keith Rothman
25680f6a07 Fix WREDUCE on FF not fixing ARST_VALUE parameter.
Adds test case that fails without code change.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-22 10:30:42 -08:00
Eddie Hung
d56f02d1fc abc9 to use AIGER symbol table, as opposed to map file 2019-02-21 17:03:40 -08:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress
Improve ABC netname preservation
2019-02-22 01:16:34 +01:00
Eddie Hung
2811d66dea Revert "abc9 to write_xaiger -symbols, not -map"
This reverts commit 04429f8152.
2019-02-21 14:58:40 -08:00
Eddie Hung
7ad9628f07 Remove irrelevant citations 2019-02-21 14:41:11 -08:00
Eddie Hung
085ed9f487 Add attribution 2019-02-21 14:40:13 -08:00
Eddie Hung
875a02a6f2 abc9 to not select anything extra, and pop selection after final clean 2019-02-21 14:38:52 -08:00
Eddie Hung
04429f8152 abc9 to write_xaiger -symbols, not -map 2019-02-21 14:28:36 -08:00
Eddie Hung
3307295488 Merge branch 'read_aiger' into xaig 2019-02-21 14:27:32 -08:00
Eddie Hung
7f8f36273a abc9 to use &mfs 2019-02-21 13:16:24 -08:00
Eddie Hung
a8803a1519 Merge remote-tracking branch 'origin/master' into xaig 2019-02-21 11:23:00 -08:00
Eddie Hung
6b96df41bc abc9 to only disconnect output ports of AND and NOT gates 2019-02-21 11:15:47 -08:00
Clifford Wolf
d55790909c Hotfix for 4c82ddf
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 19:27:23 +01:00
Keith Rothman
4c82ddf394 Add -params mode to force undef parameters in selected cells.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-21 10:16:38 -08:00
Clifford Wolf
0e371109b0
Merge pull request #818 from YosysHQ/clifford/dffsrfix
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
2019-02-21 18:58:44 +01:00
Clifford Wolf
893194689d Fix typo in passes/pmgen/README.md
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:50:02 +01:00
Eddie Hung
be061810d7 Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig 2019-02-21 09:31:17 -08:00
Clifford Wolf
2da4c9c8f0 Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:49:45 +01:00
Clifford Wolf
2fe1c830eb Bugfix in ice40_dsp
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:28:46 +01:00
Eddie Hung
7f26043caf ABC -> ABC9 2019-02-20 17:36:57 -08:00
Eddie Hung
e5b8bb9faa abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_ 2019-02-20 17:33:35 -08:00
Eddie Hung
32853b1f8d lut/not/and suffix to be ${lut,not,and} 2019-02-20 16:30:30 -08:00
Eddie Hung
2ca83005fb abc9 to cope with multiple modules 2019-02-20 12:56:15 -08:00
Eddie Hung
d6b317b349 abc9 to use & syntax for -fast, and name fixes 2019-02-20 12:40:17 -08:00
Clifford Wolf
218e9051bb Add "synth_ice40 -dsp"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:42:27 +01:00
Clifford Wolf
246391200e Add FF support to wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:36:42 +01:00
Clifford Wolf
dca65d83a0 Detect and reject cases that do not map well to iCE40 DSPs (yet)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 11:18:19 +01:00
Eddie Hung
62e5ff9ba8 abc9 to cope with indexed wires when creating $lut from $_NOT_ 2019-02-19 16:06:03 -08:00
Jim Lawson
5c4a72c43e Fix normal (non-array) hierarchy -auto-top.
Add simple test.
2019-02-19 14:35:15 -08:00
Eddie Hung
8158bc3f99 abc9 to replace $_NOT_ with $lut 2019-02-19 12:30:20 -08:00
Clifford Wolf
5a853ed46c Add actual DSP inference to ice40_dsp pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-17 15:35:48 +01:00
Clifford Wolf
c06c062469 Merge branch 'master' of github.com:YosysHQ/yosys into pmgen 2019-02-17 12:10:19 +01:00
Eddie Hung
45d49d5d14 Get rid of debugging stuff in abc9 2019-02-16 22:25:22 -08:00
Eddie Hung
f853b2f3c1 abc9 to write_aiger with -O option, and ignore dummy outputs 2019-02-16 20:09:40 -08:00
Eddie Hung
d8c4d4e6c7 abc9 to handle comb loops, cope with constant outputs, disconnect using new wire 2019-02-16 13:47:38 -08:00
Eddie Hung
e7c7ab8fc0 expose command to not skip 'internal' wires beginning with '$' 2019-02-16 13:45:17 -08:00
Eddie Hung
d4545d415b abc9 to cope with non-wideports, count cells properly 2019-02-16 08:53:06 -08:00
Eddie Hung
f8d0134598 Move lookup inside if 2019-02-15 15:23:26 -08:00
Eddie Hung
a786ac4d53 Refactor 2019-02-15 13:00:13 -08:00
Eddie Hung
914546efd9 Cope with width != 1 when re-mapping cells 2019-02-15 12:55:52 -08:00
Eddie Hung
956ee545c5 abc9 to stitch results with CI/CO properly 2019-02-15 11:52:34 -08:00
Jim Lawson
5c504c5ae6 Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code). 2019-02-15 11:31:37 -08:00