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https://github.com/YosysHQ/yosys
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Add actual DSP inference to ice40_dsp pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
c06c062469
commit
5a853ed46c
3 changed files with 214 additions and 24 deletions
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@ -24,6 +24,180 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void create_ice40_dsp(ice40_dsp_pm &pm)
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{
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#if 0
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log("\n");
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log("ffA: %s\n", log_id(pm.st.ffA, "--"));
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log("ffB: %s\n", log_id(pm.st.ffB, "--"));
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log("mul: %s\n", log_id(pm.st.mul, "--"));
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log("ffY: %s\n", log_id(pm.st.ffY, "--"));
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log("addAB: %s\n", log_id(pm.st.addAB, "--"));
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log("muxAB: %s\n", log_id(pm.st.muxAB, "--"));
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log("ffS: %s\n", log_id(pm.st.ffS, "--"));
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#endif
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log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(pm.st.mul));
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if (GetSize(pm.st.sigA) > 16) {
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log(" input A (%s) is too large (%d > 16).\n", log_signal(pm.st.sigA), GetSize(pm.st.sigA));
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return;
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}
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if (GetSize(pm.st.sigB) > 16) {
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log(" input B (%s) is too large (%d > 16).\n", log_signal(pm.st.sigB), GetSize(pm.st.sigB));
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return;
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}
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if (GetSize(pm.st.sigS) > 32) {
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log(" accumulator (%s) is too large (%d > 32).\n", log_signal(pm.st.sigS), GetSize(pm.st.sigS));
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return;
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}
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if (GetSize(pm.st.sigY) > 32) {
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log(" output (%s) is too large (%d > 32).\n", log_signal(pm.st.sigY), GetSize(pm.st.sigY));
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return;
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}
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log(" replacing $mul with SB_MAC16 cell.\n");
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bool mul_signed = pm.st.mul->getParam("\\A_SIGNED").as_bool();
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Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
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pm.module->swap_names(cell, pm.st.mul);
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// SB_MAC16 Input Interface
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SigSpec A = pm.st.sigA;
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A.extend_u0(16, mul_signed);
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SigSpec B = pm.st.sigB;
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B.extend_u0(16, mul_signed);
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SigSpec CD;
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if (pm.st.muxA)
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CD = pm.st.muxA->getPort("\\B");
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if (pm.st.muxB)
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CD = pm.st.muxB->getPort("\\A");
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CD.extend_u0(32, mul_signed);
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cell->setPort("\\A", A);
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cell->setPort("\\B", B);
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cell->setPort("\\C", CD.extract(0, 16));
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cell->setPort("\\D", CD.extract(16, 16));
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cell->setParam("\\A_REG", pm.st.ffA ? State::S0 : State::S1);
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cell->setParam("\\B_REG", pm.st.ffB ? State::S0 : State::S1);
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cell->setPort("\\AHOLD", State::S0);
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cell->setPort("\\BHOLD", State::S0);
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cell->setPort("\\CHOLD", State::S0);
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cell->setPort("\\DHOLD", State::S0);
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cell->setPort("\\IRSTTOP", State::S0);
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cell->setPort("\\IRSTBOT", State::S0);
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if (pm.st.clock_vld)
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{
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cell->setPort("\\CLK", pm.st.clock);
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cell->setPort("\\CE", State::S1);
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cell->setParam("\\NEG_TRIGGER", pm.st.clock_pol ? State::S0 : State::S1);
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log(" clock: %s (%s)", log_signal(pm.st.clock), pm.st.clock_pol ? "posedge" : "negedge");
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if (pm.st.ffA)
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log(" ffA:%s", log_id(pm.st.ffA));
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if (pm.st.ffB)
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log(" ffB:%s", log_id(pm.st.ffB));
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if (pm.st.ffY)
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log(" ffY:%s", log_id(pm.st.ffY));
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if (pm.st.ffS)
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log(" ffS:%s", log_id(pm.st.ffS));
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log("\n");
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}
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else
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{
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cell->setPort("\\CLK", State::S0);
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cell->setPort("\\CE", State::S0);
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cell->setParam("\\NEG_TRIGGER", State::S0);
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}
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// SB_MAC16 Cascade Interface
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cell->setPort("\\SIGNEXTIN", State::Sx);
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cell->setPort("\\SIGNEXTOUT", pm.module->addWire(NEW_ID));
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cell->setPort("\\CI", State::Sx);
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cell->setPort("\\CO", pm.module->addWire(NEW_ID));
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cell->setPort("\\ACCUMCI", State::Sx);
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cell->setPort("\\ACCUMCO", pm.module->addWire(NEW_ID));
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// SB_MAC16 Output Interface
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SigSpec O = pm.st.ffS ? pm.st.sigS : pm.st.sigY;
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if (GetSize(O) < 32)
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O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
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cell->setPort("\\O", O);
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if (pm.st.addAB) {
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log(" accumulator %s (%s)\n", log_id(pm.st.addAB), log_id(pm.st.addAB->type));
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cell->setPort("\\ADDSUBTOP", pm.st.addAB->type == "$add" ? State::S0 : State::S1);
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cell->setPort("\\ADDSUBBOT", pm.st.addAB->type == "$add" ? State::S0 : State::S1);
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} else {
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cell->setPort("\\ADDSUBTOP", State::S0);
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cell->setPort("\\ADDSUBBOT", State::S0);
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}
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cell->setPort("\\ORTSTOP", State::S0);
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cell->setPort("\\ORTSBOT", State::S0);
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cell->setPort("\\OHOLDTOP", State::S0);
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cell->setPort("\\OHOLDBOT", State::S0);
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SigSpec acc_reset = State::S0;
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if (pm.st.muxA)
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acc_reset = pm.st.muxA->getPort("\\S");
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if (pm.st.muxB)
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acc_reset = pm.module->Not(NEW_ID, pm.st.muxB->getPort("\\S"));
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cell->setPort("\\OLOADTOP", acc_reset);
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cell->setPort("\\OLOADBOT", acc_reset);
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// SB_MAC16 Remaining Parameters
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cell->setParam("\\C_REG", State::S0);
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cell->setParam("\\D_REG", State::S0);
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cell->setParam("\\TOP_8x8_MULT_REG", pm.st.ffY ? State::S1 : State::S0);
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cell->setParam("\\BOT_8x8_MULT_REG", pm.st.ffY ? State::S1 : State::S0);
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cell->setParam("\\PIPELINE_16X16_MULT_REG1", pm.st.ffY ? State::S1 : State::S0);
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cell->setParam("\\PIPELINE_16X16_MULT_REG2", State::S0);
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cell->setParam("\\TOPOUTPUT_SELECT", Const(pm.st.ffS ? 1 : 3, 2));
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cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
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cell->setParam("\\TOPADDSUB_UPPERINPUT", State::S0);
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cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
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cell->setParam("\\BOTOUTPUT_SELECT", Const(pm.st.ffS ? 1 : 3, 2));
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cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
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cell->setParam("\\BOTADDSUB_UPPERINPUT", State::S0);
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cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
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cell->setParam("\\MODE_8x8", State::S0);
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cell->setParam("\\A_SIGNED", mul_signed ? State::S1 : State::S0);
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cell->setParam("\\B_SIGNED", mul_signed ? State::S1 : State::S0);
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pm.autoremove(pm.st.mul);
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pm.autoremove(pm.st.ffY);
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pm.autoremove(pm.st.ffS);
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}
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struct Ice40DspPass : public Pass {
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Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { }
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void help() YS_OVERRIDE
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@ -32,7 +206,7 @@ struct Ice40DspPass : public Pass {
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log("\n");
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log(" ice40_dsp [options] [selection]\n");
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log("\n");
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log("Map multipliers and iCE40 DSP resources.\n");
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log("Map multipliers and multiply-accumulate blocks to iCE40 DSP resources.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -51,26 +225,7 @@ struct Ice40DspPass : public Pass {
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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ice40_dsp_pm pm(module, module->selected_cells());
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pm.run([&]()
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{
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log("\n");
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log("ffA: %s\n", log_id(pm.st.ffA, "--"));
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log("ffB: %s\n", log_id(pm.st.ffB, "--"));
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log("mul: %s\n", log_id(pm.st.mul, "--"));
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log("ffY: %s\n", log_id(pm.st.ffY, "--"));
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log("addAB: %s\n", log_id(pm.st.addAB, "--"));
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log("muxAB: %s\n", log_id(pm.st.muxAB, "--"));
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log("ffS: %s\n", log_id(pm.st.ffS, "--"));
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pm.blacklist(pm.st.mul);
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pm.blacklist(pm.st.ffA);
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pm.blacklist(pm.st.ffB);
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pm.blacklist(pm.st.ffY);
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pm.blacklist(pm.st.ffS);
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});
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}
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ice40_dsp_pm(module, module->selected_cells()).run(create_ice40_dsp);
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}
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} Ice40DspPass;
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@ -63,7 +63,7 @@ code sigY clock clock_pol clock_vld
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sigY = port(mul, \Y);
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if (ffY) {
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sigY = port(ffY, \D);
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sigY = port(ffY, \Q);
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SigBit c = port(ffY, \CLK).as_bit();
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bool cp = param(ffY, \CLK_POLARITY).as_bool();
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@ -77,7 +77,7 @@ code sigY clock clock_pol clock_vld
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endcode
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match addA
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select addA->type.in($add, $sub)
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select addA->type.in($add)
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select nusers(port(addA, \A)) == 2
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index <SigSpec> port(addA, \A) === sigY
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optional
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@ -134,3 +134,17 @@ match ffS
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index <SigSpec> port(ffS, \D) === port(muxAB, \Y)
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index <SigSpec> port(ffS, \Q) === sigS
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endmatch
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code clock clock_pol clock_vld
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if (ffS) {
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SigBit c = port(ffS, \CLK).as_bit();
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bool cp = param(ffS, \CLK_POLARITY).as_bool();
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if (clock_vld && (c != clock || cp != clock_pol))
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reject;
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clock = c;
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clock_pol = cp;
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clock_vld = true;
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}
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endcode
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@ -203,6 +203,7 @@ with open("%s_pm.h" % prefix, "w") as f:
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print(" dict<index_{}_key_type, vector<Cell*>> index_{};".format(index, index), file=f)
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print(" dict<SigBit, pool<Cell*>> sigusers;", file=f)
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print(" pool<Cell*> blacklist_cells;", file=f)
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print(" pool<Cell*> autoremove_cells;", file=f)
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print(" bool blacklist_dirty;", file=f)
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print(" int rollback;", file=f)
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print("", file=f)
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@ -244,6 +245,15 @@ with open("%s_pm.h" % prefix, "w") as f:
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print(" }", file=f)
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print("", file=f)
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print(" void autoremove(Cell *cell) {", file=f)
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print(" if (cell != nullptr) {", file=f)
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print(" if (blacklist_cells.insert(cell).second)", file=f)
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print(" blacklist_dirty = true;", file=f)
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print(" autoremove_cells.insert(cell);", file=f)
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print(" }", file=f)
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print(" }", file=f)
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print("", file=f)
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print(" void check_blacklist() {", file=f)
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print(" if (!blacklist_dirty)", file=f)
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print(" return;", file=f)
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@ -308,7 +318,13 @@ with open("%s_pm.h" % prefix, "w") as f:
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print(" }", file=f)
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print("", file=f)
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print(" void run(std::function<void()> on_accept_f) {{".format(prefix), file=f)
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print(" ~{}_pm() {{".format(prefix), file=f)
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print(" for (auto cell : autoremove_cells)", file=f)
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print(" module->remove(cell);", file=f)
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print(" }", file=f)
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print("", file=f)
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print(" void run(std::function<void()> on_accept_f) {", file=f)
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print(" on_accept = on_accept_f;", file=f)
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print(" rollback = 0;", file=f)
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print(" blacklist_dirty = false;", file=f)
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@ -321,6 +337,11 @@ with open("%s_pm.h" % prefix, "w") as f:
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print(" }", file=f)
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print("", file=f)
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print(" void run(std::function<void({}_pm&)> on_accept_f) {{".format(prefix), file=f)
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print(" run([&](){on_accept_f(*this);});", file=f)
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print(" }", file=f)
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print("", file=f)
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for index in range(len(blocks)):
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block = blocks[index]
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