Claire Xenia Wolf
e151e44caa
Improvements in "viz" command
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 19:32:31 +01:00
Claire Xenia Wolf
c9f4b06cb2
Add "viz" pass for visualizing big-picture data flow in larger designs
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 11:35:10 +01:00
Dag Lem
22090011ab
Made make_struct_member_range side-effect-free again
2022-12-04 06:54:22 +01:00
Claire Xenia Wolf
92fc6cd4a9
Add splitcells pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 01:33:04 +01:00
Claire Xenia Wolf
8895b51dbb
Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff
2022-12-04 00:20:44 +01:00
Dag Lem
f94eec952f
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
Miodrag Milanovic
34a64aa322
set VERI-1063 explicitly
2022-12-02 17:11:17 +01:00
Jannis Harder
0f7b8b8d23
tcl: Don't exit repl on recoverable command errors
2022-12-02 15:50:41 +01:00
Jannis Harder
5524d5185d
tcl: Return scratchpad result.json and result.string as tcl objects
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This makes it possible for yosys commands to return values when invoked
as tcl commands. Right now no commands natively support this, but the
tee command can be used with json output like this:
```tcl
set stat [yosys tee -q -s result.json stat -json -top top]
dict get $stat modules \\top num_cells_by_type \$pmux
```
Or with newline separated lists like this:
```tcl
split [yosys tee -q -s result.string select -list top] "\n"
```
2022-12-02 14:36:19 +01:00
Jannis Harder
7036a312bf
stat: Fix JSON output for empty designs
2022-12-02 14:36:19 +01:00
Jannis Harder
ed02d52f30
tee: Allow logging command output to a given scratchpad value
2022-12-02 14:36:19 +01:00
Miodrag Milanović
a64ed824ed
Merge pull request #3567 from YosysHQ/tcl_fix_crash
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Fix tcl crash in case of error executing command
2022-12-02 08:15:31 +01:00
Claire Xenia Wolf
956b7f5fd1
Merge branch 'xprop' of github.com:jix/yosys into claire/eqystuff
2022-12-01 11:31:39 +01:00
Claire Xenia Wolf
fbf8bcf38f
Add insbuf -chain mode
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-01 10:02:35 +01:00
github-actions[bot]
dcc1cb7ddd
Bump version
2022-12-01 00:20:32 +00:00
Jannis Harder
4a2b7287ca
Merge pull request #3551 from daglem/struct-array-swapped-range
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Support for arrays with swapped ranges within structs
2022-12-01 00:58:32 +01:00
Dag Lem
64f88eb7f1
Added asserts for current limitation of array dimensions in packed structs
2022-11-30 23:32:41 +01:00
Dag Lem
15c8e74329
Check for all cases of currently unsupported array dimensions in packed structs
2022-11-30 20:04:45 +01:00
Jannis Harder
eb0039848b
miter: Add -make_cover option to cover each output pair difference
2022-11-30 19:01:28 +01:00
Jannis Harder
551ca7f97f
formalff: Fix -ff2anyinit assertion error for fine FFs
2022-11-30 19:01:28 +01:00
Jannis Harder
ce708122a5
New xprop pass to encode 3-valued x-propagation using 2-valued logic
2022-11-30 19:01:28 +01:00
Jannis Harder
5ff69a0fe2
sim: Improved global clock handling
2022-11-30 18:50:53 +01:00
Jannis Harder
3ecf85e32c
opt_expr: Optimizations for $bweqx and $bwmux
2022-11-30 18:50:53 +01:00
Jannis Harder
be752a20dc
Add bwmuxmap pass
2022-11-30 18:50:53 +01:00
Jannis Harder
7203ba7bc1
Add bitwise $bweqx and $bwmux cells
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The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
2022-11-30 18:24:35 +01:00
Jannis Harder
f2c531e65f
verilog_backend: Do not run bmuxmap or demuxmap in -noexpr mode.
2022-11-30 18:24:35 +01:00
Jannis Harder
82b630a246
verilog_backend: Correctly sign extend output of signed $modfloor
2022-11-30 18:24:35 +01:00
Jannis Harder
5cb7d0fe9d
verilog_backend: Add -noparallelcase option
2022-11-30 18:24:35 +01:00
Jannis Harder
99163fb822
simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal
2022-11-30 18:24:35 +01:00
Jannis Harder
605d127517
simlib: Silence iverilog warning for $lut
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iverilog complains about implicitly truncating LUT when connecting it to
the `$bmux` A input. This explicitly truncates it to avoid that warning
without changing the behaviour otherwise.
2022-11-30 18:24:35 +01:00
Jannis Harder
39ac113402
simlib: Fix wide $bmux and avoid iverilog warnings
2022-11-30 18:24:35 +01:00
Jannis Harder
b982ab4f59
satgen, simlib: Consistent x-propagation for $pmux cells
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This updates satgen and simlib to use a `$pmux` model where the output
is fully X when the S input is not all zero or one-hot with no x bits.
2022-11-30 18:24:35 +01:00
Jannis Harder
1e67c3a3c2
opt_expr: Fix shift/shiftx optimizations
2022-11-30 18:24:25 +01:00
Miodrag Milanovic
2dd55d73a0
reset elaboration error after rewriter
2022-11-30 17:26:48 +01:00
Miodrag Milanovic
bfd79845b6
Set all verific messages of certain type to other
2022-11-30 16:42:37 +01:00
Miodrag Milanovic
b0469b3863
Fix tcl crash in case of error executing command
2022-11-30 15:54:31 +01:00
Jannis Harder
fd56d1f79e
opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cells
2022-11-29 19:06:45 +01:00
Jannis Harder
c08242ba41
opt_expr: Optimize bitwise logic ops with one fully const input
2022-11-29 19:06:45 +01:00
Jannis Harder
661fa5ff92
simplemap: Map $xnor to $_XNOR_ cells
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The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of
the `$_XNOR_` cell.
2022-11-29 19:06:45 +01:00
github-actions[bot]
f9db7c0599
Bump version
2022-11-29 00:18:02 +00:00
Jannis Harder
10e22608c0
Merge pull request #3565 from jix/sat-def-formal
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sat: Add -set-def-formal option to force defined $any* outputs
2022-11-28 16:04:38 +01:00
Jannis Harder
ed0e14820e
sat: Add -set-def-formal option to force defined $any* outputs
2022-11-28 14:50:52 +01:00
github-actions[bot]
23e26ff661
Bump version
2022-11-26 00:16:21 +00:00
Miodrag Milanović
fd01d9eb8b
Merge pull request #3561 from YosysHQ/tcl_shell
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Add TCL interactive shell mode
2022-11-25 18:12:43 +01:00
Miodrag Milanović
448a796e15
Merge pull request #3560 from YosysHQ/verific_conf
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Support importing verilog configurations using Verific
2022-11-25 17:40:57 +01:00
Miodrag Milanovic
2450e6be22
Add TCL interactive shell mode
2022-11-25 16:18:02 +01:00
Miodrag Milanovic
f764cd1655
update documentation
2022-11-25 14:27:30 +01:00
Miodrag Milanovic
b0be19c126
Support importing verilog configurations using Verific
2022-11-25 13:02:11 +01:00
github-actions[bot]
c55c514cdb
Bump version
2022-11-25 00:16:25 +00:00
KrystalDelusion
b9b5899cce
Remove docs dependency on yosys repo ( #3558 )
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* Copies guidelines files into docs/ for website
* Copying manual/CHAPTER_Prog for new docs
* Copying manual/APPNOTE_011... for new docs
Also adding faketime to list of packages for website build.
Co-authored-by: KrystalDelusion <krystinedawn@yosyshq.com>
2022-11-24 15:56:44 +01:00
