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https://github.com/YosysHQ/yosys
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Add splitcells pass
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf
parent
8895b51dbb
commit
92fc6cd4a9
2 changed files with 192 additions and 0 deletions
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@ -13,6 +13,7 @@ OBJS += passes/cmds/connect.o
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OBJS += passes/cmds/scatter.o
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OBJS += passes/cmds/setundef.o
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OBJS += passes/cmds/splitnets.o
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OBJS += passes/cmds/splitcells.o
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OBJS += passes/cmds/stat.o
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OBJS += passes/cmds/setattr.o
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OBJS += passes/cmds/copy.o
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191
passes/cmds/splitcells.cc
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191
passes/cmds/splitcells.cc
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@ -0,0 +1,191 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SplitcellsWorker
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{
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Module *module;
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SigMap sigmap;
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dict<SigBit, tuple<IdString,IdString,int>> bit_drivers_db;
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dict<SigBit, pool<tuple<IdString,IdString,int>>> bit_users_db;
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SplitcellsWorker(Module *module) : module(module), sigmap(module)
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{
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for (auto cell : module->cells()) {
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for (auto conn : cell->connections()) {
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if (!cell->output(conn.first)) continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit(sigmap(conn.second[i]));
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bit_drivers_db[bit] = tuple<IdString,IdString,int>(cell->name, conn.first, i);
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}
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}
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}
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for (auto cell : module->cells()) {
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for (auto conn : cell->connections()) {
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if (!cell->input(conn.first)) continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit(sigmap(conn.second[i]));
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if (!bit_drivers_db.count(bit)) continue;
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bit_users_db[bit].insert(tuple<IdString,IdString,int>(cell->name,
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conn.first, i-std::get<2>(bit_drivers_db[bit])));
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}
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}
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}
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for (auto wire : module->wires()) {
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if (!wire->name.isPublic()) continue;
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SigSpec sig(sigmap(wire));
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for (int i = 0; i < GetSize(sig); i++) {
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SigBit bit(sig[i]);
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if (!bit_drivers_db.count(bit)) continue;
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bit_users_db[bit].insert(tuple<IdString,IdString,int>(wire->name,
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IdString(), i-std::get<2>(bit_drivers_db[bit])));
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}
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}
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}
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int split(Cell *cell, const std::string &format)
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{
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if (!cell->type.in("$and", "$mux", "$not", "$or", "$pmux", "$xnor", "$xor")) return 0;
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SigSpec outsig = sigmap(cell->getPort(ID::Y));
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if (GetSize(outsig) <= 1) return 0;
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std::vector<int> slices;
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slices.push_back(0);
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for (int i = 1; i < GetSize(outsig); i++) {
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auto &last_users = bit_users_db.at(outsig[slices.back()]);
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auto &this_users = bit_users_db.at(outsig[i]);
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if (last_users != this_users) slices.push_back(i);
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}
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if (GetSize(slices) <= 1) return 0;
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slices.push_back(GetSize(outsig));
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log("Splitting %s cell %s/%s into %d slices:\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(slices)-1);
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for (int i = 1; i < GetSize(slices); i++)
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{
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int slice_msb = slices[i]-1;
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int slice_lsb = slices[i-1];
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IdString slice_name = module->uniquify(cell->name.str() + (slice_msb == slice_lsb ?
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stringf("%c%d%c", format[0], slice_lsb, format[1]) :
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stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1])));
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Cell *slice = module->addCell(slice_name, cell);
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auto slice_signal = [&](SigSpec old_sig) -> SigSpec {
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SigSpec new_sig;
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for (int i = 0; i < GetSize(old_sig); i += GetSize(outsig))
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new_sig.append(old_sig.extract(i+slice_lsb, slice_msb-slice_lsb+1));
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return new_sig;
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};
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slice->setPort(ID::A, slice_signal(slice->getPort(ID::A)));
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if (slice->hasParam(ID::A_WIDTH))
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slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(ID::A)));
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if (slice->hasPort(ID::B)) {
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slice->setPort(ID::B, slice_signal(slice->getPort(ID::B)));
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if (slice->hasParam(ID::B_WIDTH))
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slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(ID::B)));
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}
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slice->setPort(ID::Y, slice_signal(slice->getPort(ID::Y)));
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if (slice->hasParam(ID::Y_WIDTH))
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slice->setParam(ID::Y_WIDTH, GetSize(slice->getPort(ID::Y)));
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if (slice->hasParam(ID::WIDTH))
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slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Y)));
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log(" slice %d: %s => %s\n", i, log_id(slice_name), log_signal(slice->getPort(ID::Y)));
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}
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module->remove(cell);
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return GetSize(slices)-1;
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}
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};
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struct SplitcellsPass : public Pass {
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SplitcellsPass() : Pass("splitcells", "split up multi-bit cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" splitcells [options] [selection]\n");
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log("\n");
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log("This command splits multi-bit cells into smaller chunks, based on usage of the\n");
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log("cell output bits.\n");
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log("\n");
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log("This command operates only in cells such as $or, $and, and $mux, that are easily\n");
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log("cut into bit-slices.\n");
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log("\n");
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log(" -format char1[char2[char3]]\n");
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log(" the first char is inserted between the cell name and the bit index, the\n");
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log(" second char is appended to the cell name. e.g. -format () creates cell\n");
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log(" names like 'mycell(42)'. the 3rd character is the range separation\n");
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log(" character when creating multi-bit cells. the default is '[]:'.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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std::string format;
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log_header(design, "Executing SPLITCELLS pass (splitting up multi-bit cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-format" && argidx+1 < args.size()) {
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format = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (GetSize(format) < 1) format += "[";
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if (GetSize(format) < 2) format += "]";
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if (GetSize(format) < 3) format += ":";
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for (auto module : design->selected_modules())
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{
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SplitcellsWorker worker(module);
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int count_split_pre = 0;
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int count_split_post = 0;
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for (auto cell : module->selected_cells()) {
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int n = worker.split(cell, format);
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count_split_pre += (n != 0);
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count_split_post += n;
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}
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if (count_split_pre)
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log("Split %d cells in module %s into %d cell slices.\n",
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count_split_pre, log_id(module), count_split_post);
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}
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}
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} SplitnetsPass;
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PRIVATE_NAMESPACE_END
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