18 commits

Author	SHA1	Message	Date
Miodrag Milanovic	0d60902fd9	hierarchy - proc reorder	2019-10-18 09:04:02 +02:00
Miodrag Milanovic	7785f23719	Check latches type one by one	2019-10-04 10:31:51 +02:00
Miodrag Milanovic	3358b2f185	Removed top module where not needed	2019-10-04 09:53:54 +02:00
Miodrag Milanovic	3c40c81030	Test muxes synth one by one	2019-10-04 08:52:54 +02:00
Miodrag Milanovic	d6ef9b1a6b	Cleaned verilog code from not used defines	2019-10-04 08:45:58 +02:00
Miodrag Milanovic	abb5a3a44d	Check for MULT18X18D, since that is working now	2019-10-04 08:44:10 +02:00
Miodrag Milanovic	9e8175fc75	Check flops one by one	2019-10-04 08:42:29 +02:00
Miodrag Milanovic	d19f765a58	Removed alu and div_mod tests as agreed	2019-10-04 08:41:53 +02:00
Eddie Hung	1caaf51492	equiv_opt with -assert	2019-09-30 19:54:59 -07:00
Eddie Hung	f8d5e11aa7	Update resource count for alu.ys	2019-09-30 19:54:04 -07:00
Eddie Hung	d992858318	Move $x to end as per 7f0eec8	2019-09-30 15:15:14 -07:00
Eddie Hung	eeb86247c5	Update fsm.ys resource count	2019-09-30 15:14:41 -07:00
SergeyDegtyar	5eb91fa69f	Add comment to dpram test about related issue.	2019-09-18 12:16:04 +03:00
SergeyDegtyar	c597c2f2ae	adffs test update (equiv_opt -multiclock). div_mod test fix	2019-09-17 12:19:31 +03:00
SergeyDegtyar	93f305b1c5	Remove stat command form shifter.ys test	2019-09-04 14:57:45 +03:00
SergeyDegtyar	a203c8569c	Fix ecp5 tests ... - remove *_synth.v files and generation in scripts; - change synth_ice40 to synth_ecp5;	2019-09-04 12:15:52 +03:00
SergeyDegtyar	55fbc1a355	Uncomment sat command in memory.ys test.	2019-09-03 12:11:12 +03:00
SergeyDegtyar	11f330ed22	Add tests for ECP5 architecture	2019-09-03 11:53:37 +03:00