mirror of
https://github.com/YosysHQ/yosys
synced 2025-05-20 14:04:03 +00:00
Fix ecp5 tests
- remove *_synth.v files and generation in scripts; - change synth_ice40 to synth_ecp5;
This commit is contained in:
SergeyDegtyar
parent
55fbc1a355
commit
a203c8569c
11 changed files with 26 additions and 2421 deletions
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@ -2,10 +2,12 @@ read_verilog alu.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 62 t:SB_CARRY
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select -assert-count 32 t:SB_DFF
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select -assert-count 655 t:SB_LUT4
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select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
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select -assert-count 32 t:CCU2C
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select -assert-count 253 t:L6MUX21
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select -assert-count 1150 t:LUT4
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select -assert-count 423 t:PFUMX
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select -assert-count 32 t:TRELLIS_FF
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select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D
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@ -2,10 +2,9 @@ read_verilog counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 6 t:SB_CARRY
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select -assert-count 8 t:SB_DFFR
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select -assert-count 8 t:SB_LUT4
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select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D
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select -assert-count 4 t:CCU2C
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select -assert-count 8 t:TRELLIS_FF
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select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D
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@ -15,4 +15,3 @@ design -load postopt
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cd top
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select -assert-count 1 t:DP16KD
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select -assert-none t:DP16KD %% t:* %D
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write_verilog dpram_synth.v
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@ -1,165 +0,0 @@
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/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */
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(* dynports = 1 *)
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(* top = 1 *)
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(* src = "dpram.v:4" *)
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module top(din, write_en, waddr, wclk, raddr, rclk, dout);
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(* unused_bits = "8" *)
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wire [8:0] _0_;
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(* src = "dpram.v:8" *)
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input [7:0] din;
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(* src = "dpram.v:10" *)
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output [7:0] dout;
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(* src = "dpram.v:7" *)
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input [7:0] raddr;
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(* src = "dpram.v:9" *)
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input rclk;
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(* src = "dpram.v:7" *)
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input [7:0] waddr;
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(* src = "dpram.v:9" *)
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input wclk;
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(* src = "dpram.v:9" *)
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input write_en;
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(* module_not_derived = 32'd1 *)
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(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/brams_map.v:79" *)
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DP16KD #(
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.CLKAMUX("CLKA"),
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.CLKBMUX("CLKB"),
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.DATA_WIDTH_A(32'sd9),
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.DATA_WIDTH_B(32'sd9),
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.GSR("DISABLED"),
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.INITVAL_00(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_01(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_02(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_03(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_04(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_05(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_06(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_07(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_08(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_09(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_10(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_11(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_12(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_13(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_14(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_15(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_16(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_17(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_18(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_19(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_1A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_1B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_1C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_1D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_1E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_1F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_20(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_21(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_22(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_23(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_24(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_25(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_26(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_27(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_28(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_29(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_2A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_2B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_2C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_2D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_2E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_2F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_30(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_31(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_32(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_33(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_34(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_35(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_36(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_37(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_38(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_39(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_3A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_3B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_3C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_3D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_3E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_3F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.WRITEMODE_A("READBEFOREWRITE"),
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.WRITEMODE_B("READBEFOREWRITE")
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) \mem.0.0.0 (
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.ADA0(1'h0),
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.ADA1(1'h0),
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.ADA10(waddr[7]),
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.ADA11(1'h0),
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.ADA12(1'h0),
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.ADA13(1'h0),
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.ADA2(1'h0),
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.ADA3(waddr[0]),
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.ADA4(waddr[1]),
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.ADA5(waddr[2]),
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.ADA6(waddr[3]),
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.ADA7(waddr[4]),
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.ADA8(waddr[5]),
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.ADA9(waddr[6]),
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.ADB0(1'h0),
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.ADB1(1'h0),
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.ADB10(raddr[7]),
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.ADB11(1'h0),
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.ADB12(1'h0),
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.ADB13(1'h0),
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.ADB2(1'h0),
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.ADB3(raddr[0]),
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.ADB4(raddr[1]),
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.ADB5(raddr[2]),
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.ADB6(raddr[3]),
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.ADB7(raddr[4]),
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.ADB8(raddr[5]),
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.ADB9(raddr[6]),
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.CEA(1'h1),
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.CEB(1'h1),
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.CLKA(wclk),
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.CLKB(rclk),
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.DIA0(din[0]),
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.DIA1(din[1]),
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.DIA10(1'h0),
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.DIA11(1'h0),
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.DIA12(1'h0),
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.DIA13(1'h0),
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.DIA14(1'h0),
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.DIA15(1'h0),
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.DIA16(1'h0),
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.DIA17(1'h0),
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.DIA2(din[2]),
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.DIA3(din[3]),
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.DIA4(din[4]),
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.DIA5(din[5]),
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.DIA6(din[6]),
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.DIA7(din[7]),
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.DIA8(1'h0),
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.DIA9(1'h0),
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.DOB0(dout[0]),
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.DOB1(dout[1]),
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.DOB2(dout[2]),
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.DOB3(dout[3]),
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.DOB4(dout[4]),
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.DOB5(dout[5]),
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||||
.DOB6(dout[6]),
|
||||
.DOB7(dout[7]),
|
||||
.DOB8(_0_[8]),
|
||||
.OCEA(1'h1),
|
||||
.OCEB(1'h1),
|
||||
.RSTA(1'h0),
|
||||
.RSTB(1'h0),
|
||||
.WEA(write_en),
|
||||
.WEB(1'h0)
|
||||
);
|
||||
assign _0_[7:0] = dout;
|
||||
endmodule
|
||||
|
|
@ -2,12 +2,13 @@ read_verilog fsm.v
|
|||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
|
||||
#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 2 t:SB_DFFESR
|
||||
select -assert-count 2 t:SB_DFFSR
|
||||
select -assert-count 1 t:SB_DFFSS
|
||||
select -assert-count 13 t:SB_LUT4
|
||||
select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D
|
||||
select -assert-count 1 t:L6MUX21
|
||||
select -assert-count 15 t:LUT4
|
||||
select -assert-count 6 t:PFUMX
|
||||
select -assert-count 6 t:TRELLIS_FF
|
||||
select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D
|
||||
|
|
|
|||
|
|
@ -14,4 +14,3 @@ cd top
|
|||
select -assert-count 4 t:LUT4
|
||||
select -assert-count 1 t:PFUMX
|
||||
select -assert-none t:LUT4 t:PFUMX %% t:* %D
|
||||
write_verilog latches_synth.v
|
||||
|
|
|
|||
|
|
@ -1,109 +0,0 @@
|
|||
/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */
|
||||
|
||||
(* top = 1 *)
|
||||
(* src = "latches.v:27" *)
|
||||
module top(clk, clr, pre, a, b, b1, b2);
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *)
|
||||
wire _0_;
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *)
|
||||
wire _1_;
|
||||
(* src = "latches.v:31" *)
|
||||
input a;
|
||||
(* src = "latches.v:32" *)
|
||||
output b;
|
||||
(* src = "latches.v:32" *)
|
||||
output b1;
|
||||
(* src = "latches.v:32" *)
|
||||
output b2;
|
||||
(* src = "latches.v:28" *)
|
||||
input clk;
|
||||
(* src = "latches.v:29" *)
|
||||
input clr;
|
||||
(* src = "latches.v:30" *)
|
||||
input pre;
|
||||
(* src = "latches.v:43|latches.v:9" *)
|
||||
wire \u_latchn.d ;
|
||||
(* src = "latches.v:43|latches.v:9" *)
|
||||
wire \u_latchn.en ;
|
||||
(* src = "latches.v:43|latches.v:9" *)
|
||||
wire \u_latchn.q ;
|
||||
(* src = "latches.v:36|latches.v:2" *)
|
||||
wire \u_latchp.d ;
|
||||
(* src = "latches.v:36|latches.v:2" *)
|
||||
wire \u_latchp.en ;
|
||||
(* src = "latches.v:36|latches.v:2" *)
|
||||
wire \u_latchp.q ;
|
||||
(* src = "latches.v:50|latches.v:16" *)
|
||||
wire \u_latchsr.clr ;
|
||||
(* src = "latches.v:50|latches.v:16" *)
|
||||
wire \u_latchsr.d ;
|
||||
(* src = "latches.v:50|latches.v:16" *)
|
||||
wire \u_latchsr.en ;
|
||||
(* src = "latches.v:50|latches.v:16" *)
|
||||
wire \u_latchsr.pre ;
|
||||
(* src = "latches.v:50|latches.v:16" *)
|
||||
wire \u_latchsr.q ;
|
||||
(* module_not_derived = 32'd1 *)
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:106" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h5150)
|
||||
) _2_ (
|
||||
.A(clr),
|
||||
.B(clk),
|
||||
.C(pre),
|
||||
.D(b2),
|
||||
.Z(_0_)
|
||||
);
|
||||
(* module_not_derived = 32'd1 *)
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:108" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h5554)
|
||||
) _3_ (
|
||||
.A(clr),
|
||||
.B(clk),
|
||||
.C(pre),
|
||||
.D(b2),
|
||||
.Z(_1_)
|
||||
);
|
||||
(* module_not_derived = 32'd1 *)
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:110" *)
|
||||
PFUMX _4_ (
|
||||
.ALUT(_1_),
|
||||
.BLUT(_0_),
|
||||
.C0(a),
|
||||
.Z(b2)
|
||||
);
|
||||
(* module_not_derived = 32'd1 *)
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *)
|
||||
LUT4 #(
|
||||
.INIT(16'bx1x1x1x0x0x1x0x0)
|
||||
) _5_ (
|
||||
.A(1'h0),
|
||||
.B(clk),
|
||||
.C(b),
|
||||
.D(a),
|
||||
.Z(b)
|
||||
);
|
||||
(* module_not_derived = 32'd1 *)
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *)
|
||||
LUT4 #(
|
||||
.INIT(16'bx1x1x0x1x1x0x0x0)
|
||||
) _6_ (
|
||||
.A(1'h0),
|
||||
.B(clk),
|
||||
.C(b1),
|
||||
.D(a),
|
||||
.Z(b1)
|
||||
);
|
||||
assign \u_latchn.d = a;
|
||||
assign \u_latchn.en = clk;
|
||||
assign \u_latchn.q = b1;
|
||||
assign \u_latchp.d = a;
|
||||
assign \u_latchp.en = clk;
|
||||
assign \u_latchp.q = b;
|
||||
assign \u_latchsr.clr = clr;
|
||||
assign \u_latchsr.d = a;
|
||||
assign \u_latchsr.en = clk;
|
||||
assign \u_latchsr.pre = pre;
|
||||
assign \u_latchsr.q = b2;
|
||||
endmodule
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
read_verilog logic.v
|
||||
hierarchy -top top
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 9 t:SB_LUT4
|
||||
select -assert-none t:SB_LUT4 %% t:* %D
|
||||
select -assert-count 9 t:LUT4
|
||||
select -assert-none t:LUT4 %% t:* %D
|
||||
|
|
|
|||
|
|
@ -17,4 +17,3 @@ select -assert-count 32 t:PFUMX
|
|||
select -assert-count 8 t:TRELLIS_DPR16X4
|
||||
select -assert-count 35 t:TRELLIS_FF
|
||||
select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
|
||||
write_verilog memory_synth.v
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -2,8 +2,9 @@ read_verilog shifter.v
|
|||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 8 t:SB_DFF
|
||||
select -assert-none t:SB_DFF %% t:* %D
|
||||
stat
|
||||
select -assert-count 8 t:TRELLIS_FF
|
||||
select -assert-none t:TRELLIS_FF %% t:* %D
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue