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Author	SHA1	Message	Date
Emil J. Tywoniak	a582aceaca	opt_expr: replace invert_map with signorm traversal	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	3010c0fc31	signorm: add timers	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	fb06c1add5	rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	061cec3166	check: fix memory bug in $connect	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	25e7118e4a	memory_bram: create blackboxes	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	8042d0dc77	Revert "intel: register bram celltypes" ... This reverts commit 16785a7f75af3a9d7be9f6450edbb927ce873d4a.	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	eaa67e8d36	Revert "tests: use memory -bram-register in tests/bram" ... This reverts commit 24488a7011474080bcb99a91d38ae27b2c2d813c.	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	76d8b2c2ea	Revert "memory: add -bram-register" ... This reverts commit 2bc6ea7f37f5c239491e83a3a8672af8954550ab.	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	6f09e55c95	Revert "memory_bram: add -register" ... This reverts commit b4b5093a14e5dceded852c644e70bf6ff447bba3.	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	1f745fb781	intel_alm: loosen tests	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	7cad14da7d	gowin: loosen tests	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	c8208db681	flatten: disable signorm	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	cc1bd1d4f1	ecp5: loosen tests	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	3de496e0c4	nexus: loosen tests	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	e313678594	xilinx_dsp: signorm compatibility	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	2291084045	pmgen: hold sigmap pointer instead of owning it	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	92475ecf62	equiv_miter: don't copy $input_port	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	83fa720157	rtlil_bufnorm: more xlog	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	15bd3bcfad	design: properly switch signorm mode when restoring saved designs	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	52ae92380d	equiv_make: don't copy $input_port	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	360527af1a	rtlil: fix cloneInto in signorm	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	2fc93aa711	rtlil: sigNormalize Module when added to Design in signorm mode	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	f7149450b4	rtlil_bufnorm: more xlog	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	1b19859e84	intel: register bram celltypes	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	c40974ee59	rtlil_bufnorm: ignore timing info harder	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	0c64152d7a	gowin: replace positional arguments in cells_sim.v with named	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	b0e9dab15a	Revert "techmap: call hierarchy on map files to determine port directions" ... This reverts commit eabbf6d22527f386811c7b507f74f887a258b397.	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	6ca6d4281f	hierarchy: tolerance for apparent recursive instances in techmap files	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	e82e1aeaad	techmap: call hierarchy on map files to determine port directions	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	71f01b23f8	tests: use memory -bram-register in tests/bram	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	eecab792a3	memory: add -bram-register	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	5b836f1b2b	memory_bram: add -register	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	8bcec792e2	ffmerge: initvals signorm compatibility fixup	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	3b1e79d312	timinginfo: special-case $specify2 in signorm invariant	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	de7f38087d	opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	79386f652f	connect: remove input ports on conflict	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	f4d180e78f	opt_dff: sigma harder, FfDataSigMapped	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	aeaf095be4	ff: add FfDataSigMapped	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	df94483b9f	opt_dff: temporarily disable signorm due to muxtree traversal	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	e6dc9b4aba	tests: fix rtlil roundtrip test	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	f06d67a031	design: fix signorm commit connectivity to design	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	9c3704d5a4	cxxrtl: ignore $input_port	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	728fe21917	flatten: redo signormalization to work around fanout issue	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	2869f5bf9c	abstract: fix test signorm	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	b3baa75528	signorm: disable passes that use rewrite_sigspecs	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	246bd6c1f2	aiger: ignore $input_port	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	7528cb3157	check: stitch info about $connect ports together for driver analysis	2026-07-17 23:32:53 +02:00
Emil J. Tywoniak	9cc0997658	signorm: remove $input cells when leaving	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	23e37193b4	abstract: skip $input_port cells	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	1350c0da92	flatten: skip $input_port cells in template module	2026-07-17 23:32:34 +02:00