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Author	SHA1	Message	Date
Eddie Hung	6bd9550100	ice40: add delays to SB_CARRY	2020-02-27 10:17:29 -08:00
Eddie Hung	3b74e0fa45	xilinx: add delays to INV	2020-02-27 10:17:29 -08:00
Eddie Hung	6bb3d9f9c0	Make TimingInfo::TimingInfo(SigBit) constructor explicit	2020-02-27 10:17:29 -08:00
Eddie Hung	9dcf204dec	TimingInfo: index by (port_name,offset)	2020-02-27 10:17:29 -08:00
Eddie Hung	7c3b4b80ea	Fix spacing	2020-02-27 10:17:29 -08:00
Eddie Hung	aa969f8778	More +/ice40/cells_sim.v fixes	2020-02-27 10:17:29 -08:00
Eddie Hung	f858219c4e	Cleanup tests	2020-02-27 10:17:29 -08:00
Eddie Hung	717fb492b3	Update bug1630.ys to use -lut 4 instead of lut file	2020-02-27 10:17:29 -08:00
Eddie Hung	b0ffd9cd8b	Make +/xilinx/cells_sim.v legal	2020-02-27 10:17:29 -08:00
Eddie Hung	d6cff77751	abc9_ops: still emit delay table even box has no timing	2020-02-27 10:17:29 -08:00
Eddie Hung	5ff60d2057	write_xaiger: add comment about arrival times of flop outputs	2020-02-27 10:17:29 -08:00
Eddie Hung	683c5ce940	abc9_ops: demote lack of box timing info to warning	2020-02-27 10:17:29 -08:00
Eddie Hung	1ef1ca812b	Get rid of (* abc9_{arrival,required} *) entirely	2020-02-27 10:17:29 -08:00
Eddie Hung	a6fec9fe60	abc9_ops: use TimingInfo for -prep_{lut,box} too	2020-02-27 10:17:29 -08:00
Eddie Hung	3ea5506f81	abc9_ops: use TimingInfo for -prep_{lut,box} too	2020-02-27 10:17:29 -08:00
Eddie Hung	cda4acb544	abc9_ops: add and use new TimingInfo struct	2020-02-27 10:17:29 -08:00
Eddie Hung	bc97e64b21	Fix tests/arch/xilinx/fsm.ys to count flops only	2020-02-27 10:17:29 -08:00
Eddie Hung	7d86aceee3	Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy	2020-02-27 10:17:29 -08:00
Eddie Hung	3728ef1765	ice40: fix specify for inverted clocks	2020-02-27 10:17:29 -08:00
Eddie Hung	aac309626b	Fix tests by gating some specify constructs from iverilog	2020-02-27 10:17:29 -08:00
Eddie Hung	977262c803	Update simple_abc9 tests	2020-02-27 10:17:29 -08:00
Eddie Hung	e22fee6cdd	abc9_ops: ignore (* abc9_flop *) if not '-dff'	2020-02-27 10:17:29 -08:00
Eddie Hung	a76520112d	ice40: specify fixes	2020-02-27 10:17:29 -08:00
Eddie Hung	7c92b6852f	abc9_ops: sort LUT delays to be ascending	2020-02-27 10:17:29 -08:00
Eddie Hung	fb60d82971	ice40: move over to specify blocks for -abc9	2020-02-27 10:17:29 -08:00
Eddie Hung	a85c55113f	synth_ecp5: use +/abc9_model.v	2020-02-27 10:17:29 -08:00
Eddie Hung	8408c13405	Update xilinx for ABC9	2020-02-27 10:17:29 -08:00
Eddie Hung	ac24a23e31	Create +/abc9_model.v for $__ABC9_{DELAY,FF_}	2020-02-27 10:17:29 -08:00
Eddie Hung	7317521c6f	abc9_ops: output LUT area	2020-02-27 10:17:29 -08:00
Eddie Hung	d2284715fa	ecp5: remove small LUT entries	2020-02-27 10:17:29 -08:00
Eddie Hung	0ed550d83c	abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs	2020-02-27 10:17:29 -08:00
Eddie Hung	ccc84f8923	Fix commented out specify statement	2020-02-27 10:17:29 -08:00
Eddie Hung	12d70ca8fb	xilinx: improve specify functionality	2020-02-27 10:17:29 -08:00
Eddie Hung	46a89d7264	ecp5: deprecate abc9_{arrival,required} and *.{lut,box}	2020-02-27 10:17:29 -08:00
Eddie Hung	577545488a	xilinx: use specify blocks in place of abc9_{arrival,required}	2020-02-27 10:17:29 -08:00
Eddie Hung	0e7c55e2a7	Auto-generate .box/.lut files from specify blocks	2020-02-27 10:17:29 -08:00
Eddie Hung	3d6603792d	abc9_ops: assert on $specify2 properties	2020-02-27 10:17:29 -08:00
Eddie Hung	74f49b1f55	abc9_ops: -prep_box, to be called once	2020-02-27 10:17:29 -08:00
Eddie Hung	5643c1b8c5	abc9_ops: -prep_lut and -write_lut to auto-generate LUT library	2020-02-27 10:17:29 -08:00
Claire Wolf	ab8826ae36	Merge pull request #1709 from rqou/coolrunner2_counter ... Improve CoolRunner-II optimization by using extract_counter pass	2020-02-27 19:05:56 +01:00
Claire Wolf	47228feb77	Merge pull request #1708 from rqou/coolrunner2-buf-fix ... coolrunner2: Separate and improve buffer cell insertion pass	2020-02-27 19:03:59 +01:00
Piotr Binkowski	62ab100c61	xilinx: mark IOBUFDSE3 IOB pin as external	2020-02-27 13:15:57 +01:00
Miodrag Milanović	036c46de1e	Merge pull request #1705 from YosysHQ/logger_pass ... Logger pass	2020-02-26 13:32:49 +01:00
Miodrag Milanovic	80656ad178	Remove tests for now	2020-02-26 09:49:41 +01:00
Alberto Gonzalez	f80fe8dc22	Change attribute search value to specify precise location instead of simple line number.	2020-02-24 02:41:08 +00:00
Alberto Gonzalez	2c2f092c90	Change attribute search value to specify precise location instead of simple line number.	2020-02-24 01:39:36 +00:00
Miodrag Milanovic	c1cee15d64	Add tests for logger pass	2020-02-23 10:56:39 +01:00
Miodrag Milanovic	1c569fe06a	Remove duplicate warning detection	2020-02-23 10:56:27 +01:00
Miodrag Milanovic	48eed2860c	Fix line endings	2020-02-23 10:05:21 +01:00
Alberto Gonzalez	f0afd65035	Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.	2020-02-23 07:22:26 +00:00