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Remove tests for now

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This commit is contained in:
Miodrag Milanovic 2020-02-26 09:49:41 +01:00
parent c1cee15d64
commit 80656ad178
4 changed files with 0 additions and 24 deletions
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6
tests/various/logger_error.ys
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@ -1,6 +0,0 @@
logger -werror "is implicitly declared." -expect error "is implicitly declared." 1
read_verilog << EOF
module top(...);
assign b = w;
endmodule
EOF

6
tests/various/logger_nowarning.ys
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@ -1,6 +0,0 @@
logger -expect-no-warnings -nowarn "is implicitly declared."
read_verilog << EOF
module top(...);
assign b = w;
endmodule
EOF

6
tests/various/logger_warn.ys
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@ -1,6 +0,0 @@
logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1
read_verilog << EOF
module top(...);
assign b = w;
endmodule
EOF

6
tests/various/logger_warning.ys
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@ -1,6 +0,0 @@
logger -expect warning "is implicitly declared." 2
read_verilog << EOF
module top(...);
assign b = w;
endmodule
EOF