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abc9_ops: -prep_lut and -write_lut to auto-generate LUT library
This commit is contained in:
Eddie Hung
parent
ab8826ae36
commit
5643c1b8c5
4 changed files with 200 additions and 10 deletions
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@ -145,6 +145,11 @@ struct Abc9Pass : public ScriptPass
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log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
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log(" 2, 3, .. inputs.\n");
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log("\n");
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log(" -maxlut <width>\n");
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log(" when auto-generating the lut library, discard all luts equal to or\n");
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log(" greater than this size (applicable when neither -lut nor -luts is\n");
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log(" specified).\n");
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log("\n");
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log(" -dff\n");
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log(" also pass $_ABC9_FF_ cells through to ABC. modules with many clock\n");
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log(" domains are marked as such and automatically partitioned by ABC.\n");
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@ -175,6 +180,8 @@ struct Abc9Pass : public ScriptPass
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std::stringstream exe_cmd;
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bool dff_mode, cleanup;
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bool lut_mode;
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int maxlut;
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std::string box_file;
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void clear_flags() YS_OVERRIDE
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@ -183,6 +190,8 @@ struct Abc9Pass : public ScriptPass
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exe_cmd << "abc9_exe";
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dff_mode = false;
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cleanup = true;
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lut_mode = false;
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maxlut = 0;
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box_file.clear();
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}
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@ -204,9 +213,11 @@ struct Abc9Pass : public ScriptPass
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if ((arg == "-exe" || arg == "-script" || arg == "-D" ||
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/* arg == "-S" || */ arg == "-lut" || arg == "-luts" ||
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/*arg == "-S" ||*/ arg == "-lut" || arg == "-luts" ||
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/*arg == "-box" ||*/ arg == "-W") &&
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argidx+1 < args.size()) {
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if (arg == "-lut" || arg == "-luts")
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lut_mode = true;
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exe_cmd << " " << arg << " " << args[++argidx];
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continue;
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}
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@ -228,6 +239,10 @@ struct Abc9Pass : public ScriptPass
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box_file = args[++argidx];
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continue;
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}
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if (arg == "-maxlut" && argidx+1 < args.size()) {
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maxlut = atoi(args[++argidx].c_str());
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continue;
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}
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if (arg == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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@ -240,6 +255,9 @@ struct Abc9Pass : public ScriptPass
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}
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extra_args(args, argidx, design);
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if (maxlut && lut_mode)
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log_cmd_error("abc9 '-maxlut' option only applicable without '-lut' nor '-luts'.\n");
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log_assert(design);
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if (design->selected_modules().empty()) {
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log_warning("No modules selected for ABC9 techmapping.\n");
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@ -263,6 +281,10 @@ struct Abc9Pass : public ScriptPass
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run("abc9_ops -mark_scc -prep_delays -prep_xaiger [-dff]", "(option for -dff)");
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else
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run("abc9_ops -mark_scc -prep_delays -prep_xaiger" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
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if (help_mode)
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run("abc9_ops -prep_lut <maxlut>", "(skip if -lut or -luts)");
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else if (!lut_mode)
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run(stringf("abc9_ops -prep_lut %d", maxlut));
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run("select -set abc9_holes A:abc9_holes");
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run("flatten -wb @abc9_holes");
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run("techmap @abc9_holes");
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@ -276,9 +298,10 @@ struct Abc9Pass : public ScriptPass
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if (check_label("map")) {
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if (help_mode) {
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run("foreach module in selection");
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run(" abc9_ops -write_lut <abc-temp-dir>/input.lut", "(skip if '-lut' or '-luts')");
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run(" abc9_ops -write_box [<value from -box>|(null)] <abc-temp-dir>/input.box");
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run(" write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig");
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run(" abc9_exe [options] -cwd <abc-temp-dir> -box <abc-temp-dir>/input.box");
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run(" abc9_exe [options] -cwd <abc-temp-dir> [-lut <abc-temp-dir>/input.lut] -box <abc-temp-dir>/input.box");
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run(" read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
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run(" abc9_ops -reintegrate");
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}
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@ -304,6 +327,8 @@ struct Abc9Pass : public ScriptPass
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tempdir_name[0] = tempdir_name[4] = '_';
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tempdir_name = make_temp_dir(tempdir_name);
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if (!lut_mode)
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run(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str()));
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if (box_file.empty())
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run(stringf("abc9_ops -write_box (null) %s/input.box", tempdir_name.c_str()));
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else
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@ -319,7 +344,12 @@ struct Abc9Pass : public ScriptPass
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active_design->scratchpad_get_int("write_xaiger.num_inputs"),
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num_outputs);
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if (num_outputs) {
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run(stringf("%s -cwd %s -box %s/input.box", exe_cmd.str().c_str(), tempdir_name.c_str(), tempdir_name.c_str()));
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std::string abc9_exe_cmd;
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abc9_exe_cmd += stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str());
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if (!lut_mode)
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abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name.c_str());
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abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name.c_str());
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run(abc9_exe_cmd);
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run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str()));
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run("abc9_ops -reintegrate");
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}
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@ -562,6 +562,56 @@ void prep_delays(RTLIL::Design *design)
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design->scratchpad_set_string("abc9_ops.box.flops", ss.str());
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}
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void prep_lut(RTLIL::Design *design, int maxlut)
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{
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std::stringstream ss;
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std::vector<std::pair<int, std::string>> table;
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for (auto module : design->modules()) {
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auto it = module->attributes.find(ID(abc9_lut));
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if (it == module->attributes.end())
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continue;
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SigBit o;
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std::vector<int> specify;
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for (auto cell : module->cells()) {
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if (cell->type != ID($specify2))
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continue;
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log_assert(cell->getParam(ID(SRC_WIDTH)) == 1);
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log_assert(cell->getParam(ID(DST_WIDTH)) == 1);
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SigBit d = cell->getPort(ID(DST));
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if (o == SigBit())
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o = d;
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else
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log_assert(o == d);
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int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
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int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
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specify.push_back(std::max(rise_max,fall_max));
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}
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if (maxlut && GetSize(specify) > maxlut)
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continue;
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std::sort(specify.begin(), specify.end());
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ss.str("");
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ss << "# " << module->name.str() << std::endl;
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ss << GetSize(specify) << " " << it->second.as_int();
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for (auto i : specify)
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ss << " " << i;
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ss << std::endl;
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table.emplace_back(GetSize(specify), ss.str());
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}
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// ABC expects ascending size
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std::sort(table.begin(), table.end());
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ss.str("");
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for (auto &i : table)
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ss << i.second;
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design->scratchpad_set_string("abc9_ops.lut_library", ss.str());
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}
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void write_lut(RTLIL::Module *module, const std::string &dst) {
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std::ofstream ofs(dst);
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log_assert(ofs.is_open());
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ofs << module->design->scratchpad_get_string("abc9_ops.lut_library");
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ofs.close();
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}
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void write_box(RTLIL::Module *module, const std::string &src, const std::string &dst) {
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std::ofstream ofs(dst);
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log_assert(ofs.is_open());
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@ -1002,6 +1052,12 @@ struct Abc9OpsPass : public Pass {
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log(" compute the clock domain and initial value of each flop in the design.\n");
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log(" process the '$holes' module to support clock-enable functionality.\n");
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log("\n");
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log(" -prep_lut <maxlut>\n");
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log(" pre-compute the lut library.\n");
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log("\n");
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log(" -write_lut <dst>\n");
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log(" TODO.\n");
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log("\n");
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log(" -write_box (<src>|(null)) <dst>\n");
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log(" copy the existing box file from <src> (skip if '(null)') and append any\n");
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log(" new box definitions.\n");
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@ -1021,8 +1077,11 @@ struct Abc9OpsPass : public Pass {
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bool mark_scc_mode = false;
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bool prep_dff_mode = false;
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bool prep_xaiger_mode = false;
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bool prep_lut_mode = false;
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bool reintegrate_mode = false;
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bool dff_mode = false;
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std::string write_lut_dst;
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int maxlut = 0;
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std::string write_box_src, write_box_dst;
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size_t argidx;
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@ -1048,6 +1107,19 @@ struct Abc9OpsPass : public Pass {
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prep_delays_mode = true;
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continue;
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}
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if (arg == "-prep_lut" && argidx+1 < args.size()) {
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prep_lut_mode = true;
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maxlut = atoi(args[++argidx].c_str());
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continue;
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}
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if (arg == "-write_lut" && argidx+1 < args.size()) {
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write_lut_dst = args[++argidx];
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rewrite_filename(write_lut_dst);
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continue;
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}
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if (arg == "-maxlut" && argidx+1 < args.size()) {
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continue;
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}
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if (arg == "-write_box" && argidx+2 < args.size()) {
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write_box_src = args[++argidx];
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write_box_dst = args[++argidx];
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@ -1067,16 +1139,21 @@ struct Abc9OpsPass : public Pass {
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}
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extra_args(args, argidx, design);
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if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || !write_box_src.empty() || reintegrate_mode))
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log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff}, -write_box, -reintegrate must be specified.\n");
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if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
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log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut}, -write_{lut,box}, -reintegrate must be specified.\n");
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if (dff_mode && !prep_xaiger_mode)
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log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
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if (maxlut && !write_lut_dst.empty())
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log_cmd_error("'-maxlut' option is only relevant for -prep_lut.\n");
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if (check_mode)
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check(design);
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if (prep_delays_mode)
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prep_delays(design);
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if (prep_lut_mode)
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prep_lut(design, maxlut);
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for (auto mod : design->selected_modules()) {
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if (mod->get_bool_attribute("\\abc9_holes"))
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@ -1090,7 +1167,9 @@ struct Abc9OpsPass : public Pass {
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if (!design->selected_whole_module(mod))
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log_error("Can't handle partially selected module %s!\n", log_id(mod));
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if (!write_box_src.empty())
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if (!write_lut_dst.empty())
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write_lut(mod, write_lut_dst);
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if (!write_box_dst.empty())
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write_box(mod, write_box_src, write_box_dst);
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if (mark_scc_mode)
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mark_scc(mod);
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@ -162,32 +162,55 @@ module INV(
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assign O = !I;
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endmodule
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(* abc9_lut=1 *)
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module LUT1(output O, input I0);
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parameter [1:0] INIT = 0;
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assign O = I0 ? INIT[1] : INIT[0];
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specify
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(I0 => O) = 127;
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endspecify
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endmodule
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(* abc9_lut=2 *)
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module LUT2(output O, input I0, I1);
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parameter [3:0] INIT = 0;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 238;
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(I1 => O) = 127;
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endspecify
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endmodule
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(* abc9_lut=3 *)
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module LUT3(output O, input I0, I1, I2);
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parameter [7:0] INIT = 0;
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 407;
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(I1 => O) = 238;
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(I2 => O) = 127;
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endspecify
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endmodule
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(* abc9_lut=3 *)
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module LUT4(output O, input I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 472;
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(I1 => O) = 407;
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(I2 => O) = 238;
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(I3 => O) = 127;
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endspecify
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endmodule
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(* abc9_lut=3 *)
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module LUT5(output O, input I0, I1, I2, I3, I4);
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parameter [31:0] INIT = 0;
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wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
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@ -195,8 +218,16 @@ module LUT5(output O, input I0, I1, I2, I3, I4);
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 631;
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(I1 => O) = 472;
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(I2 => O) = 407;
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(I3 => O) = 238;
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(I4 => O) = 127;
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endspecify
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endmodule
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(* abc9_lut=5 *)
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module LUT6(output O, input I0, I1, I2, I3, I4, I5);
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parameter [63:0] INIT = 0;
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wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
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@ -205,6 +236,14 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5);
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 642;
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(I1 => O) = 631;
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(I2 => O) = 472;
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(I3 => O) = 407;
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(I4 => O) = 238;
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(I5 => O) = 127;
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endspecify
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endmodule
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module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
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@ -223,6 +262,50 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
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assign O5 = I0 ? s5_1[1] : s5_1[0];
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endmodule
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(* abc9_lut=10 *)
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module $__ABC9_LUT7(output O, input I0, I1, I2, I3, I4, I5, I6);
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parameter [127:0] INIT = 0;
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wire [63: 0] s6 = I6 ? INIT[127:64] : INIT[63: 0];
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wire [31: 0] s5 = I5 ? s6[63:32] : s6[31: 0];
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wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 1028;
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(I1 => O) = 1017;
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(I2 => O) = 858;
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(I3 => O) = 793;
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(I4 => O) = 624;
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(I5 => O) = 513;
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(I6 => O) = 464;
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endspecify
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endmodule
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(* abc9_lut=20 *)
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module $__ABC9_LUT8(output O, input I0, I1, I2, I3, I4, I5, I6, I7);
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parameter [255:0] INIT = 0;
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wire [127: 0] s7 = I7 ? INIT[255:128] : INIT[127: 0];
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wire [ 63: 0] s6 = I6 ? s7[127:63] : s7[ 64: 0];
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wire [ 31: 0] s5 = I5 ? s6[ 63:32] : s6[ 31: 0];
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wire [ 15: 0] s4 = I4 ? s5[ 31:16] : s5[ 15: 0];
|
||||
wire [ 7: 0] s3 = I3 ? s4[ 15: 8] : s4[ 7: 0];
|
||||
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
|
||||
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
|
||||
assign O = I0 ? s1[1] : s1[0];
|
||||
specify
|
||||
(I0 => O) = 1149;
|
||||
(I1 => O) = 1138;
|
||||
(I2 => O) = 979;
|
||||
(I3 => O) = 914;
|
||||
(I4 => O) = 745;
|
||||
(I5 => O) = 634;
|
||||
(I6 => O) = 585;
|
||||
(I7 => O) = 468;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
module MUXCY(output O, input CI, DI, S);
|
||||
assign O = S ? CI : DI;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -354,7 +354,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
std::string read_args;
|
||||
if (vpr)
|
||||
read_args += " -D_EXPLICIT_CARRY";
|
||||
read_args += " -lib +/xilinx/cells_sim.v";
|
||||
read_args += " -lib -specify +/xilinx/cells_sim.v";
|
||||
run("read_verilog" + read_args);
|
||||
|
||||
run("read_verilog -lib +/xilinx/cells_xtra.v");
|
||||
|
|
@ -627,9 +627,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
else
|
||||
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
|
||||
if (nowidelut)
|
||||
abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
|
||||
else
|
||||
abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
|
||||
abc9_opts += stringf(" -maxlut %d", lut_size_s);
|
||||
if (dff_mode)
|
||||
abc9_opts += " -dff";
|
||||
run("abc9" + abc9_opts);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue