423 commits

Author	SHA1	Message	Date
Eddie Hung	a270af00cc	Put abc_* attributes above port	2019-08-23 11:21:44 -07:00
Eddie Hung	33960dd3d8	Merge pull request #1209 from YosysHQ/eddie/synth_xilinx ... [WIP] synth xilinx renaming, as per #1184	2019-08-20 12:55:26 -07:00
Eddie Hung	d9fe4cccbf	Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx	2019-08-20 11:57:52 -07:00
Eddie Hung	d81a090d89	Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro	2019-08-19 09:56:17 -07:00
Eddie Hung	562c9e3624	Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules	2019-08-16 15:40:53 -07:00
Eddie Hung	48d0f99406	stoi -> atoi	2019-08-07 11:09:17 -07:00
Eddie Hung	66806085db	RST -> RSTBRST for RAMB8BWER	2019-07-29 16:05:44 -07:00
David Shah	ab607e896e	xilinx: Fix missing cell name underscore in cells_map.v ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-25 08:19:07 +01:00
Eddie Hung	43616e1414	Update Makefile too	2019-07-18 14:51:55 -07:00
Eddie Hung	b97fe6e866	Work in progress for renaming labels/options in synth_xilinx	2019-07-18 14:20:43 -07:00
Eddie Hung	19c1c3cfa3	Merge pull request #1182 from koriakin/xc6s-bram ... synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 12:55:35 -07:00
Marcin Kościelnicki	a9efacd01d	xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 21:13:12 +02:00
Marcin Kościelnicki	ce250b341c	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
Eddie Hung	bb2144ae73	Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime ... Error out if -abc9 and -retime specified	2019-07-10 14:38:13 -07:00
Eddie Hung	6bbd286e03	Error out if -abc9 and -retime specified	2019-07-10 12:47:48 -07:00
Eddie Hung	58bb84e5b2	Add some spacing	2019-07-10 12:32:33 -07:00
Eddie Hung	521971e32e	Add some ASCII art explaining mux decomposition	2019-07-10 12:20:04 -07:00
Eddie Hung	e573d024a2	Call muxpack and pmux2shiftx before cmp2lut	2019-07-09 21:26:38 -07:00
Eddie Hung	c55530b901	Restore opt_clean back to original place	2019-07-09 14:29:58 -07:00
Eddie Hung	5b48b18d29	Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6	2019-07-09 14:28:54 -07:00
Eddie Hung	b1a048a703	Extend using A[1] to preserve don't care	2019-07-09 12:35:41 -07:00
Eddie Hung	93522b0ae1	Extend during mux decomposition with 1'bx	2019-07-09 10:59:37 -07:00
Eddie Hung	c864995343	Fix typo and comments	2019-07-09 10:38:07 -07:00
Eddie Hung	c91cb73562	Merge remote-tracking branch 'origin/master' into xc7mux	2019-07-09 10:22:49 -07:00
Eddie Hung	c68b909210	synth_xilinx to call commands of synth -coarse directly	2019-07-09 10:21:54 -07:00
Eddie Hung	737340327f	Revert "synth_xilinx to call "synth -run coarse" with "-keepdc"" ... This reverts commit 7f964859ec.	2019-07-09 10:15:02 -07:00
Eddie Hung	bc84f7dd10	Fix spacing	2019-07-09 09:22:12 -07:00
Eddie Hung	667199d460	Fix spacing	2019-07-09 09:16:00 -07:00
Eddie Hung	6951e32070	Decompose mux inputs in delay-orientated (rather than area) fashion	2019-07-08 23:51:13 -07:00
Eddie Hung	45da3ada7b	Do not call opt -mux_undef (part of -full) before muxcover	2019-07-08 23:49:16 -07:00
Eddie Hung	d4ab43d940	Add one more comment	2019-07-08 23:05:48 -07:00
Eddie Hung	939a225f92	Less thinking	2019-07-08 23:02:57 -07:00
Eddie Hung	de40453553	Reword	2019-07-08 22:56:19 -07:00
Eddie Hung	7f964859ec	synth_xilinx to call "synth -run coarse" with "-keepdc"	2019-07-08 19:23:24 -07:00
Eddie Hung	3f86407cc3	Map $__XILINX_SHIFTX in a more balanced manner	2019-07-08 17:06:35 -07:00
Eddie Hung	78914e2e0e	Capitalisation	2019-07-08 17:06:22 -07:00
Eddie Hung	baf47e496f	Add synth_xilinx -widemux recommended value	2019-07-08 17:04:39 -07:00
Eddie Hung	895ca50173	Fixes for 2:1 muxes	2019-07-08 12:03:38 -07:00
Eddie Hung	0944acf3af	synth_xilinx -widemux=2 is minimum now	2019-07-08 11:29:21 -07:00
Eddie Hung	dbe1326573	Parametric muxcover costs as per @daveshah1	2019-07-08 11:08:20 -07:00
Eddie Hung	c58998a7d2	atoi -> stoi as per @daveshah1	2019-07-08 10:48:10 -07:00
Eddie Hung	810f8c5dbd	Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup	2019-07-02 09:21:02 -07:00
Eddie Hung	2ea6083b7e	Fix $__XILINX_MUXF78 box timing	2019-07-01 14:04:06 -07:00
Eddie Hung	09ac274716	Revert "Fix broken MUXFx box, use MUXF7x2 box instead" ... This reverts commit a9a140aa6c.	2019-07-01 14:01:09 -07:00
Eddie Hung	a9a140aa6c	Fix broken MUXFx box, use MUXF7x2 box instead	2019-07-01 13:36:27 -07:00
Eddie Hung	85f1c2dcbe	Cleanup SRL inference/make more consistent	2019-06-29 21:42:20 -07:00
Eddie Hung	62ba724ccb	Merge remote-tracking branch 'origin/master' into xc7mux	2019-06-29 19:39:27 -07:00
Eddie Hung	dd8d264bf5	install *_nowide.lut files	2019-06-29 19:37:04 -07:00
Eddie Hung	728839d6ca	Remove peepopt call in synth_xilinx since already in synth -run coarse	2019-06-28 12:53:38 -07:00
Eddie Hung	ea0f7c9be9	Restore $__XILINX_MUXF78 const optimisation	2019-06-28 12:12:41 -07:00