Eddie Hung
278533fe59
Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire
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RFC: techmap to recognise wires named "_TECHMAP_REPLACE_.<suffix>"
2019-10-02 19:40:39 -07:00
Eddie Hung
e4bd5aaebf
Fix test
2019-10-02 18:12:25 -07:00
Eddie Hung
c6a55d948a
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
2019-10-02 18:07:38 -07:00
Eddie Hung
f6fabc8fda
Update test
2019-10-02 18:03:45 -07:00
Eddie Hung
d99810ad8a
Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-02 18:01:45 -07:00
Eddie Hung
e730a595ee
Add test
2019-10-02 18:01:41 -07:00
Eddie Hung
62c66406ad
log_dump() to support State enum
2019-10-02 17:49:07 -07:00
Eddie Hung
f46ac1df9f
Be mindful that sigmap(wire) could have dupes when checking \init
2019-10-02 16:08:46 -07:00
Eddie Hung
c28d4b8047
Add test that is expecting to fail
2019-10-02 14:52:40 -07:00
Eddie Hung
265a655ef9
Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf
2019-10-02 12:43:35 -07:00
Eddie Hung
a4f2f7d23c
Extend test with renaming cells with prefix too
2019-10-02 12:43:18 -07:00
Clifford Wolf
6028f5df1a
Merge pull request #1428 from YosysHQ/clifford/fixbtor
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Fix btor back-end to use "state" instead of "input" for undef init bits
2019-10-02 13:48:09 +02:00
Clifford Wolf
45e4c040d7
Add "check -mapped"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-02 13:35:03 +02:00
Clifford Wolf
a84a2d74c7
Fix btor back-end to use "state" instead of "input" for undef init bits
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-02 12:48:04 +02:00
Miodrag Milanović
da347b9f7e
Merge pull request #1426 from YosysHQ/mmicko/fix_environ
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Define environ, fixes #1424
2019-10-01 19:50:37 +02:00
Miodrag Milanovic
c026579c20
Define environ, fixes #1424
2019-10-01 18:45:07 +02:00
David Shah
b424d374db
ecp5: Fix shuffle_enable port
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-01 14:14:46 +01:00
David Shah
7a1538cd36
ecp5: Add support for mapping 36-bit wide PDP BRAMs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-01 13:46:36 +01:00
Sergey
eb750670e3
run-test.sh Move $x at end of line.
2019-10-01 11:14:12 +03:00
Sergey
e092c4ae6b
Merge branch 'master' into SergeyDegtyar/efinix
2019-10-01 11:04:32 +03:00
Sergey
d99b1e3261
Merge branch 'master' into SergeyDegtyar/anlogic
2019-10-01 10:57:09 +03:00
Sergey
fc56459746
run-test.sh Move $x at end of line.
2019-10-01 10:55:34 +03:00
Eddie Hung
1caaf51492
equiv_opt with -assert
2019-09-30 19:54:59 -07:00
Eddie Hung
f8d5e11aa7
Update resource count for alu.ys
2019-09-30 19:54:04 -07:00
Eddie Hung
369652d4b9
Add test
2019-09-30 17:20:39 -07:00
Eddie Hung
edc3780723
techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
2019-09-30 17:20:12 -07:00
Eddie Hung
8b239ee707
Add quick test
2019-09-30 15:34:04 -07:00
Eddie Hung
f2f19df2d4
Add -select option to aigmap
2019-09-30 15:26:29 -07:00
Eddie Hung
d963e8c2c6
Fix typo
2019-09-30 15:18:40 -07:00
Eddie Hung
d992858318
Move $x to end as per 7f0eec8
2019-09-30 15:15:14 -07:00
Eddie Hung
eeb86247c5
Update fsm.ys resource count
2019-09-30 15:14:41 -07:00
Eddie Hung
0bbd1b6364
Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys into eddie/pr1352
2019-09-30 14:57:55 -07:00
Eddie Hung
0a1af434e8
Fix for svinterfaces
2019-09-30 14:52:04 -07:00
Eddie Hung
08b55a20e3
module->derive() to be lazy and not touch ast if already derived
2019-09-30 14:11:01 -07:00
Eddie Hung
a274b7cc86
Update doc for equiv_opt
2019-09-30 10:59:56 -07:00
whitequark
5c5881695d
Merge pull request #1406 from whitequark/connect_rpc
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rpc: new frontend
2019-09-30 17:38:20 +00:00
Eddie Hung
ed47bd78e1
Merge pull request #1397 from btut/fix/python_wrappers_inline_constructors
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Generate Python wrappers for inline constructors
2019-09-30 10:31:57 -07:00
whitequark
99a7f39084
rpc: new frontend.
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A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.
Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
2019-09-30 15:53:11 +00:00
whitequark
8f2bdff7b9
libs: import json11.
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This commit imports the code from upstream commit
dropbox/json11@8ccf1f0c5e .
2019-09-30 15:53:11 +00:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
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Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
Clifford Wolf
7ed13297b1
Bump version
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-30 17:08:38 +02:00
Clifford Wolf
0d28e45dcb
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync
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equiv_opt to call async2sync when not -multiclock like SymbiYosys
2019-09-30 17:04:21 +02:00
Clifford Wolf
dd67e8ce73
Merge pull request #1417 from YosysHQ/clifford/fixasync2sync
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Fix $dlatch handling in async2sync
2019-09-30 17:04:03 +02:00
Clifford Wolf
10e57f3880
Fix $dlatch handling in async2sync
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-30 14:58:23 +02:00
Eddie Hung
6216e45eda
Add latch test modified from #1363
2019-09-30 12:52:43 +02:00
Eddie Hung
5b5756b91e
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00
Marcin Kościelnicki
4535f2c694
synth_xilinx: Support latches, remove used-up FF init values.
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Fixes #1387 .
2019-09-30 12:52:43 +02:00
Eddie Hung
d5f0794a53
Merge pull request #1414 from hzeller/improve-replace-with-empty-map
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Avoid work in replace() if rules empty.
2019-09-29 19:35:23 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Miodrag Milanovic
9e55b234b4
Fix reading aig files on windows
2019-09-29 15:40:37 +02:00
