8208 commits

This branch

This branch

All branches

Author	SHA1	Message	Date
Clifford Wolf	5a5cbf6458	Merge pull request #1078 from YosysHQ/eddie/muxcover_costs ... Allow muxcover costs to be changed	2019-06-08 11:31:19 +02:00
Eddie Hung	d5f0b73fd9	Update CHANGELOG	2019-06-07 17:00:36 -07:00
Eddie Hung	816b5f5891	Comment out muxpack (currently broken)	2019-06-07 16:58:57 -07:00
Eddie Hung	5a46a0b385	Fine tune aigerparse	2019-06-07 16:57:32 -07:00
Eddie Hung	1e201a9b01	Merge remote-tracking branch 'origin/master' into xc7mux	2019-06-07 16:15:19 -07:00
Eddie Hung	58f4b106f3	Merge branch 'master' into eddie/muxpack	2019-06-07 15:47:28 -07:00
Eddie Hung	2b350401c4	Fix spacing from spaces to tabs	2019-06-07 15:44:57 -07:00
Eddie Hung	f705f6a0b5	Comment O(N) -> O(N^2)	2019-06-07 15:39:12 -07:00
Eddie Hung	b959bf79c0	Add nonexcl case test, comment out two others	2019-06-07 15:35:15 -07:00
Eddie Hung	ba52d9b471	Extend ExclusiveDatabase to query SigSpec-s (for $pmux)	2019-06-07 15:34:16 -07:00
Eddie Hung	9b408838f1	Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results	2019-06-07 14:18:17 -07:00
Clifford Wolf	7395a80690	Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger ... Fix read_aiger to really get tested, and fix some uncovered read_aiger issues	2019-06-07 23:13:34 +02:00
Eddie Hung	f48c6920b7	Add read_aiger to CHANGELOG	2019-06-07 13:12:48 -07:00
Eddie Hung	1da12c5071	Add @cliffordwolf freduce testcase	2019-06-07 12:12:11 -07:00
Eddie Hung	e263bc249b	Add nonexclusive test from @cliffordwolf	2019-06-07 11:54:29 -07:00
Eddie Hung	887df8914c	Resolve @cliffordwolf comment on redundant check	2019-06-07 11:37:52 -07:00
Eddie Hung	5ab59cd59e	Resolve @cliffordwolf comment on sigmap	2019-06-07 11:36:19 -07:00
Eddie Hung	6934f4bdd5	Fix spacing (entire file is wrong anyway, will fix later)	2019-06-07 11:30:36 -07:00
Eddie Hung	d00ae1d6a8	Remove unnecessary std::getline() for ASCII	2019-06-07 11:28:25 -07:00
Eddie Hung	65924fd12f	Test *.aag too, by using *.aig as reference	2019-06-07 11:28:05 -07:00
Eddie Hung	a04521c6b7	Fix read_aiger -- create zero driver, fix init width, parse 'b'	2019-06-07 11:07:15 -07:00
Eddie Hung	abc40924ed	Use ABC to convert from AIGER to Verilog	2019-06-07 11:06:57 -07:00
Eddie Hung	ebe29b6659	Use ABC to convert AIGER to Verilog, then sat against Yosys	2019-06-07 11:05:36 -07:00
Eddie Hung	1b113a0574	Add symbols to AIGER test inputs for ABC	2019-06-07 11:05:25 -07:00
Eddie Hung	0f6e914ef6	Another muxpack test	2019-06-07 08:34:58 -07:00
Eddie Hung	30abdaf3b2	Allow muxcover costs to be changed	2019-06-07 08:34:11 -07:00
Eddie Hung	fe4394fb9a	Allow muxcover costs to be changed	2019-06-07 08:30:39 -07:00
Clifford Wolf	6d49145497	Merge pull request #1077 from YosysHQ/clifford/pr983 ... elaboration system tasks	2019-06-07 13:39:46 +02:00
Clifford Wolf	f01a61f093	Rename implicit_ports.sv test to implicit_ports.v ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-07 13:12:25 +02:00
Clifford Wolf	211d85cfcc	Fixes and cleanups in AST_TECALL handling ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-07 12:41:09 +02:00
Clifford Wolf	a3bbc5365b	Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983	2019-06-07 12:08:42 +02:00
Clifford Wolf	169de05f3b	Merge branch 'tux3-implicit_named_connection'	2019-06-07 11:53:46 +02:00
Clifford Wolf	7116621d22	Merge pull request #1076 from thasti/centos7-build-fix ... Fix pyosys-build on CentOS7	2019-06-07 11:48:33 +02:00
Clifford Wolf	a0b57f2a6f	Cleanup tux3-implicit_named_connection ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-07 11:46:16 +02:00
Clifford Wolf	b637b3109d	Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection	2019-06-07 11:41:54 +02:00
Stefan Biereigel	d018e02614	remove boost/log/exceptions.hpp from wrapper generator	2019-06-07 09:47:33 +02:00
Eddie Hung	88ae13e6a5	$__XILINX_MUX_ -> $__XILINX_SHIFTX	2019-06-06 15:32:36 -07:00
Eddie Hung	d3b7ae218b	Fix muxcover and its techmapping	2019-06-06 15:31:18 -07:00
Eddie Hung	a8c49168fb	Run muxpack and muxcover in synth_xilinx	2019-06-06 14:43:08 -07:00
Eddie Hung	7166dbe418	Remove abc_flop attributes for now	2019-06-06 14:35:38 -07:00
Eddie Hung	2223ca91b0	Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux	2019-06-06 14:22:10 -07:00
Eddie Hung	5c277c6325	Fix and test for balanced case	2019-06-06 14:21:34 -07:00
Eddie Hung	eaee250a6e	Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux	2019-06-06 14:06:59 -07:00
Eddie Hung	0a66720f6f	Fix warnings	2019-06-06 14:01:42 -07:00
Eddie Hung	ccdf989025	Support cascading $pmux.A with $mux.A and $mux.B	2019-06-06 13:51:22 -07:00
Eddie Hung	dc7b8c4b94	More cleanup	2019-06-06 12:56:34 -07:00
Eddie Hung	978fda94f6	Fix spacing	2019-06-06 12:46:42 -07:00
Eddie Hung	d2172c6846	Non chain user check using next_sig	2019-06-06 12:44:50 -07:00
Eddie Hung	705388eb24	Add non exclusive test	2019-06-06 12:44:06 -07:00
Eddie Hung	83450a9489	Move muxpack from passes/techmap to passes/opt	2019-06-06 12:15:13 -07:00