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Author SHA1 Message Date
Alberto Gonzalez 982562ff13
Use emplace() for more efficient insertion into various dicts. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez c658d9d59d
Build constant bits directly rather than constructing an object and copying its bits. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez f235f212ea
Replace std::set with pool for cell_to_inbit and outbit_to_cell. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 6294621825
Use emplace() rather than insert(). 2020-05-14 20:06:54 +00:00
Alberto Gonzalez dfcb936cd5
Clean up pseudo-private member usage and ensure range iteration uses references where possible to avoid unnecessary copies. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez a4755c50c3
Clean up extraneous buffer. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 7857782575
Replace std::map with dict for unique_bit_id. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 6d64d768b0
Replace std::map with dict for port_new2old_map, port_connmap, and cellbits_to_tplbits. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 5cb4ae4666
Replace std::map with dict for connbits_map, cell_to_inbit, and outbit_to_cell. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez c43017fc08
Replace std::map with dict for TechmapWires type. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 644e55b3d3
Replace std::map with dict for celltypeMap. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 67f4046c05
Replace std::set with pool for handled_cells and techmap_wire_names. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 64c16f8c13
Replace std::map with dict for positional_ports. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 2fb4931e5b
Add specialized hash() for type dict and use a dict instead of a std::map for techmap_cache and techmap_do_cache. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 437f3fb342
Replace std::map with dict for simplemap_mappers. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 99b586b283
Use nullptr instead of NULL in passes/techmap/techmap.cc. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 5f7f213c7f
Replace std::string and RTLIL::IdString with IdString in passes/techmap/techmap.cc. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-14 20:06:53 +00:00
Alberto Gonzalez e49fdee404
Do not modify design modules while iterating over modules(). 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 985a29ff3b
Clean up pseudo-private member usage, superfluous std::vector instantiation, and RTLIL::id2cstr() usage in passes/techmap/techmap.cc. 2020-05-14 20:06:53 +00:00
Eddie Hung 7b3a4a1fff opt_expr: Sx to Sz; spotted by @Xiretza 2020-05-14 12:14:23 -07:00
Eddie Hung 73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758 
opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
 2020-05-14 11:56:22 -07:00
Eddie Hung 425867d175 logger: clean up doc 2020-05-14 10:38:31 -07:00
Eddie Hung 02df0198b6 abc9_ops: -prep_hier to create unmap module that removes Q's (* init *) 2020-05-14 10:33:57 -07:00
Eddie Hung 13f9d65b6f abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it 2020-05-14 10:33:57 -07:00
Eddie Hung fa31e84112 Fix broken test when ignoring abc9_flop with init == 1'b1 2020-05-14 10:33:57 -07:00
Eddie Hung 97a0a04314 abc9_ops/xaiger: further reducing Module::derive() calls by ... 
replacing _all_ (* abc9_box *) instantiations with their derived types
 2020-05-14 10:33:57 -07:00
Eddie Hung e79127fceb Cleanup; reduce Module::derive() calls 2020-05-14 10:33:57 -07:00
Eddie Hung cea614f5ae ecp5: latches_map.v if *not* -asyncprld 2020-05-14 10:33:57 -07:00
Eddie Hung fdc340db8e ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v 2020-05-14 10:33:57 -07:00
Eddie Hung 39759d5f0e ecp5: fix rebase mistake 2020-05-14 10:33:57 -07:00
Eddie Hung 8d34aee3d5 abc9: update to =_$abc9_flops pattern which includes whiteboxes 2020-05-14 10:33:57 -07:00
Eddie Hung f652a9c11c abc9_ops: update docs 2020-05-14 10:33:57 -07:00
Eddie Hung ca4f8c9444 xilinx: gate specify/attributes from iverilog 2020-05-14 10:33:57 -07:00
Eddie Hung 57c478c537 abc9: only do +/abc9_map if `DFF 2020-05-14 10:33:57 -07:00
Eddie Hung 2946bb60e9 abc9: rework submod -- since it won't move (* keep *) cells 2020-05-14 10:33:56 -07:00
Eddie Hung 8cda29137e ecp5: TRELLIS_FF bypass path only in async mode 2020-05-14 10:33:56 -07:00
Eddie Hung 7146c0339e timinginfo: ignore $specify2 cells if EN is false 2020-05-14 10:33:56 -07:00
Eddie Hung 6c34945371 xilinx/ice40/ecp5: zinit requires selected wires, so select them all 2020-05-14 10:33:56 -07:00
Eddie Hung b65610fb62 abc9_ops: move assert 2020-05-14 10:33:56 -07:00
Eddie Hung ed7cb0b095 abc9: put 'aigmap' back 2020-05-14 10:33:56 -07:00
Eddie Hung a323881e15 xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells 2020-05-14 10:33:56 -07:00
Eddie Hung b3e2538a14 abc9_ops: fix bypass boxes using (* abc9_bypass *) 2020-05-14 10:33:56 -07:00
Eddie Hung d5a8aaba8c abc9_ops: tidy up, suppress error if no boxes/holes 2020-05-14 10:33:56 -07:00
Eddie Hung e2044fd9c7 abc9_ops: -prep_delays to not insert delay box if input connection is const 2020-05-14 10:33:56 -07:00
Eddie Hung 8b5fb99245 abc9_ops: cleanup; -prep_dff -> -prep_dff_submod 2020-05-14 10:33:56 -07:00
Eddie Hung 7cd3f4a79b abc9_ops: add -prep_bypass for auto bypass boxes; refactor 
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
 2020-05-14 10:33:56 -07:00
Eddie Hung bb840cca9c abc9_ops: -reintegrate to handle $_FF_; cleanup 2020-05-14 10:33:56 -07:00
Eddie Hung e357b40e7a xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarity 2020-05-14 10:33:56 -07:00
Eddie Hung 4017cc6380 aiger: -xaiger to return $_FF_ flops 2020-05-14 10:33:56 -07:00
Eddie Hung 722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00