Eddie Hung
2a8e5bf953
Merge pull request #805 from eddiehung/dff_init
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write_verilog to write initial statement for initial flop state
2019-02-19 12:32:40 -08:00
Eddie Hung
8158bc3f99
abc9 to replace $_NOT_ with $lut
2019-02-19 12:30:20 -08:00
Eddie Hung
e79df5e70e
read_aiger to create sane $lut names, and rename when renaming driving wire
2019-02-19 12:27:50 -08:00
David Shah
bb56cb738d
ecp5: Add DDRDLLA
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 19:34:37 +00:00
Eddie Hung
0b1fc46ae3
Add comment
2019-02-19 10:24:55 -08:00
Eddie Hung
54f719f446
Get rid of boost dep, fix the FIXMEs for Win32?
2019-02-19 10:19:53 -08:00
Eddie Hung
843e7fc8a7
Fix for using POSIX basename
2019-02-19 09:02:37 -08:00
David Shah
c36f15b489
ecp5: Add DELAYF/DELAYG blackboxes
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 14:10:43 +00:00
Clifford Wolf
62493c91b2
Add first draft of functional SB_MAC16 model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-19 14:47:27 +01:00
Eddie Hung
8e1dbfac3a
Missing OSX headers?
2019-02-17 20:59:53 -08:00
Eddie Hung
de1dc7947b
Revert "Missing headers for Xcode?"
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This reverts commit c23e3f0751
2019-02-17 20:59:15 -08:00
Eddie Hung
3af8d420c5
Merge branch 'dff_init' into read_aiger
2019-02-17 20:49:56 -08:00
Eddie Hung
11480b4fa3
Instead of INIT param on cells, use initial statement with hier ref as
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per @cliffordwolf
2019-02-17 12:18:12 -08:00
Eddie Hung
3d3353e020
Revert "Add INIT parameter to all ff/latch cells"
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This reverts commit 742b4e01b4
2019-02-17 12:11:52 -08:00
Eddie Hung
9268a271fb
read_aiger to ignore line after ands for ascii, not binary
2019-02-17 12:07:14 -08:00
Eddie Hung
430a7548bc
One more merge conflict
2019-02-17 11:50:55 -08:00
Eddie Hung
144c5d4359
Merge branch 'dff_init' into read_aiger
2019-02-17 11:49:13 -08:00
Eddie Hung
17cd5f759f
Merge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 11:49:06 -08:00
Eddie Hung
03a533d102
Merge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 11:44:01 -08:00
Clifford Wolf
5a853ed46c
Add actual DSP inference to ice40_dsp pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-17 15:35:48 +01:00
Clifford Wolf
c06c062469
Merge branch 'master' of github.com:YosysHQ/yosys into pmgen
2019-02-17 12:10:19 +01:00
Clifford Wolf
e45f62b0c5
Merge pull request #811 from ucb-bar/firrtlfixes
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Update cells supported for verilog to FIRRTL conversion.
2019-02-17 11:39:14 +01:00
Eddie Hung
45d49d5d14
Get rid of debugging stuff in abc9
2019-02-16 22:25:22 -08:00
Eddie Hung
82459c16c4
In read_xaiger, do not construct ConstEval for every LUT
2019-02-16 22:22:29 -08:00
Eddie Hung
30f1204721
Cleanup
2019-02-16 22:22:17 -08:00
Eddie Hung
f60cd4ff9b
read_aiger to ignore output = input of same wire; also create new output for different wire
2019-02-16 21:53:03 -08:00
Eddie Hung
76c35f80f4
Cleanup
2019-02-16 21:09:48 -08:00
Eddie Hung
6a57de9013
write_xaiger to support non-bit cell connections, and cope with COs for -O
2019-02-16 21:00:39 -08:00
Eddie Hung
f853b2f3c1
abc9 to write_aiger with -O option, and ignore dummy outputs
2019-02-16 20:09:40 -08:00
Eddie Hung
b9a305b85d
write_aiger -O to write dummy output as __dummy_o__
2019-02-16 20:08:59 -08:00
Eddie Hung
d8c4d4e6c7
abc9 to handle comb loops, cope with constant outputs, disconnect using new wire
2019-02-16 13:47:38 -08:00
Eddie Hung
1a25ec4baa
read_aiger to disable log_debug
2019-02-16 13:45:51 -08:00
Eddie Hung
e7c7ab8fc0
expose command to not skip 'internal' wires beginning with '$'
2019-02-16 13:45:17 -08:00
Eddie Hung
8f36013fac
read_xaiger() to use f.read() not readsome()
2019-02-16 08:58:25 -08:00
Eddie Hung
d4545d415b
abc9 to cope with non-wideports, count cells properly
2019-02-16 08:53:06 -08:00
Eddie Hung
0c409e6d8c
Tidy up write_xaiger
2019-02-16 08:48:33 -08:00
Eddie Hung
2c1655ae94
write_aiger() to perform CI/CO post-processing and fix symbols
2019-02-16 08:46:25 -08:00
Eddie Hung
7523c87780
read_aiger() to cope with constant outputs, mixed wideports, do cleaning
2019-02-16 08:44:11 -08:00
Eddie Hung
f8d0134598
Move lookup inside if
2019-02-15 15:23:26 -08:00
Eddie Hung
486a270415
Fixes needed for DFF circuits
2019-02-15 15:22:18 -08:00
Eddie Hung
a786ac4d53
Refactor
2019-02-15 13:00:13 -08:00
Eddie Hung
914546efd9
Cope with width != 1 when re-mapping cells
2019-02-15 12:55:52 -08:00
Jim Lawson
c245041bfe
Removed unused variables, functions.
2019-02-15 12:00:28 -08:00
Jim Lawson
34153adef4
Append (instead of over-writing) EXTRA_FLAGS
2019-02-15 11:56:51 -08:00
Eddie Hung
956ee545c5
abc9 to stitch results with CI/CO properly
2019-02-15 11:52:34 -08:00
Eddie Hung
8d757224ee
read_aiger with more asserts, and call clean
2019-02-15 11:52:05 -08:00
Eddie Hung
3ac5b65197
write_xaiger to cope with unknown cells by transforming them to CI/CO
2019-02-15 11:51:21 -08:00
Jim Lawson
5c504c5ae6
Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code).
2019-02-15 11:31:37 -08:00
Jim Lawson
fc1c9aa11f
Update cells supported for verilog to FIRRTL conversion.
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Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
2019-02-15 11:14:17 -08:00
Jim Lawson
970f854c2a
Merge remote-tracking branch 'upstream/master'
2019-02-15 08:19:27 -08:00
