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Code Activity
997 commits 94 branches 52 tags 62 MiB
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170 commits

Author SHA1 Message Date
Clifford Wolf 9992026a8d Added support for `line compiler directive 2014-03-11 14:06:57 +01:00
Clifford Wolf 5a15539c9b Improved verific command (added support for some operators) 2014-03-10 12:06:57 +01:00
Clifford Wolf c71791a1ff Improvements in verific command 2014-03-10 03:03:08 +01:00
Clifford Wolf 8d06f9f2fe Added "verific" command 2014-03-09 20:40:04 +01:00
Clifford Wolf 620d51d9f7 Bugfix in ilang frontend autoidx recovery 2014-03-07 17:19:14 +01:00
Clifford Wolf 4d07f88258 Fixed gcc compiler warning 2014-03-06 16:37:19 +01:00
Clifford Wolf 09805ee9ec Include id2ast pointers when dumping AST 2014-03-05 19:56:31 +01:00
Clifford Wolf d6a01fe412 Fixed merging of compatible wire decls in AST frontend 2014-03-05 19:55:58 +01:00
Clifford Wolf de7bd12004 Bugfix in recursive AST simplification 2014-03-05 19:45:33 +01:00
Clifford Wolf ef90236a5d Fixed vhdl2verilog temp dir name 2014-03-01 17:48:15 +01:00
Clifford Wolf 04999f4af0 Fixed vhdl2verilog help message 2014-03-01 17:47:19 +01:00
Clifford Wolf ae5032af84 Fixed bit-extending in $mux argument (use $bu0 instead of $pos) 2014-02-26 21:32:19 +01:00
Clifford Wolf 6bc94b7eb2 Don't blow up constants unneccessarily in Verilog frontend 2014-02-24 12:41:25 +01:00
Clifford Wolf f8c9143b2b Fixed bug in generation of undefs for $memwr MUXes 2014-02-22 17:08:00 +01:00
Clifford Wolf 0a60f95224 Added vhdl2verilog 2014-02-21 18:59:49 +01:00
Clifford Wolf 4bd25edcd4 Cleanups in handling of read_verilog -defer and -icells 2014-02-20 19:12:32 +01:00
Clifford Wolf 02e6f2c5be Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00
Clifford Wolf 7d7e068dd1 Added a warning note about error reporting to read_verilog help message 2014-02-16 20:20:25 +01:00
Clifford Wolf 7ac524e8e8 Improved support for constant functions 2014-02-16 13:16:38 +01:00
Clifford Wolf 118517ca5a Added ff and latch support to read_liberty 2014-02-15 19:44:19 +01:00
Clifford Wolf 96b1ebc8dc Bugfix in expression parser of read_liberty 2014-02-15 19:36:09 +01:00
Clifford Wolf 5e39e6ece2 Correctly convert constants to RTLIL (fixed undef handling) 2014-02-15 15:42:10 +01:00
Clifford Wolf 4440610d3f Added liberty frontend 2014-02-15 12:57:28 +01:00
Clifford Wolf 45d2b6ffce Be more conservative with new const-function code 2014-02-14 20:45:30 +01:00
Clifford Wolf e8af3def7f Added support for FOR loops in function calls in parameters 2014-02-14 20:33:22 +01:00
Clifford Wolf 534c1a5dd0 Created basic support for function calls in parameter values 2014-02-14 19:56:44 +01:00
Clifford Wolf cd9e8741a7 Implemented read_verilog -defer 2014-02-13 13:59:13 +01:00
Clifford Wolf 007bdff55d Added support for functions returning integer 2014-02-12 23:29:54 +01:00
Clifford Wolf 0defc86519 renamed ilang "scope error" to "ilang error" 2014-02-11 19:17:07 +01:00
Clifford Wolf fb186e6299 Improved ilang parser error messages 2014-02-09 15:35:31 +01:00
Clifford Wolf f4f230d7cc Fixed gcc compiler warnings with release build 2014-02-06 22:49:14 +01:00
Clifford Wolf aa8e754ae5 Added read_verilog -setattr 2014-02-05 11:22:10 +01:00
Clifford Wolf d267bcde4e Fixed bug in sequential sat proofs and improved handling of asserts 2014-02-04 12:46:16 +01:00
Clifford Wolf a6750b3753 Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) 2014-02-03 13:01:45 +01:00
Clifford Wolf cdd6e11af5 Added support for blanks after -I and -D in read_verilog 2014-02-02 13:06:21 +01:00
Clifford Wolf af325bf206 Fixed comment/eol parsing in ilang frontend 2014-02-01 17:28:02 +01:00
Clifford Wolf d06258f74f Added constant size expression support of sized constants 2014-02-01 13:50:23 +01:00
Clifford Wolf 4df7e03ec9 Bugfix in name resolution with generate blocks 2014-01-30 15:01:28 +01:00
Clifford Wolf 375c4dddc1 Added read_verilog -icells option 2014-01-29 00:59:28 +01:00
Clifford Wolf 0b47d907d3 Fixed handling of unsized constants in verilog frontend 2014-01-24 15:05:24 +01:00
Clifford Wolf 88fbdd4916 Fixed algorithmic complexity of AST simplification of long expressions 2014-01-20 20:25:20 +01:00
Clifford Wolf 1e67099b77 Added $assert cell 2014-01-19 14:03:40 +01:00
Clifford Wolf 9a1eb45c75 Added Verilog parser support for asserts 2014-01-19 04:18:22 +01:00
Clifford Wolf 13359d65ba Fixed parsing of verilog macros at end of line 2014-01-18 19:22:20 +01:00
Clifford Wolf 6170cfe9cd Added verilog_defaults command 2014-01-17 17:22:29 +01:00
Clifford Wolf a3d94bf888 Fixed typo in frontends/ast/simplify.cc 2014-01-12 21:04:42 +01:00
Clifford Wolf 8f11eaaca6 Added updating of RTLIL::autoidx to ilang frontend 2014-01-03 17:51:05 +01:00
Clifford Wolf fb2bf934dc Added correct handling of $memwr priority 2014-01-03 00:22:17 +01:00
Clifford Wolf 364f277afb Fixed a stupid access after delete bug 2013-12-29 20:18:22 +01:00
Clifford Wolf 1dcbba1abf Fixed parsing of non-arg macro calls followed by "(" 2013-12-27 16:25:27 +01:00