3684 commits

Author	SHA1	Message	Date
Eddie Hung	3a87dc3524	Wrap A and B in sigmap	2019-07-19 13:23:07 -07:00
Eddie Hung	31b0002e8c	Remove "top" from message	2019-07-19 13:20:45 -07:00
Eddie Hung	8791e0caac	Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp	2019-07-19 13:18:20 -07:00
Eddie Hung	bcd8027182	Also optimise MSB of $sub	2019-07-19 13:11:48 -07:00
Eddie Hung	fc0e36d1c0	wreduce for $sub	2019-07-19 12:50:21 -07:00
Eddie Hung	9ad11ea2cc	Fine tune ice40_dsp.pmg, add support for packing subsets of registers	2019-07-19 10:57:32 -07:00
Eddie Hung	8f0e796be1	Add support for ice40 signed multipliers	2019-07-19 10:38:13 -07:00
Eddie Hung	42e40dbd0a	Merge remote-tracking branch 'origin/master' into ice40dsp	2019-07-18 15:45:25 -07:00
Eddie Hung	09411dd996	ice40_dsp to accept $__MUL16X16 too	2019-07-18 15:38:28 -07:00
Eddie Hung	802470746c	Check if RHS is empty first	2019-07-18 15:22:00 -07:00
Eddie Hung	90ac147eb2	Do not autoremove ffP aor muxP	2019-07-18 15:02:41 -07:00
Eddie Hung	08fe63c61e	Improve pattern matcher to match subsets of $dffe? cells	2019-07-18 14:08:18 -07:00
Eddie Hung	79d63479ea	Improve A/B reg packing	2019-07-18 13:30:35 -07:00
Eddie Hung	e075f0dda0	Do not autoremove A/B registers since they might have other consumers	2019-07-18 13:22:22 -07:00
Eddie Hung	0727b2c902	Fix xilinx_dsp index cast	2019-07-18 13:18:04 -07:00
Eddie Hung	c76607b9bc	Wrong wildcard symbol	2019-07-18 08:14:58 -07:00
Eddie Hung	91629ee4b3	Pattern matcher to check pool of bits, not exactly	2019-07-17 12:45:25 -07:00
Eddie Hung	3f677fb0db	Signed extension	2019-07-16 15:54:07 -07:00
Eddie Hung	9616dbd125	Add support {A,B,P}REG packing	2019-07-16 14:06:32 -07:00
Eddie Hung	5939b5d636	Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters ... abc9: push inverters driving box inputs (comb outputs) through $lut soft logic	2019-07-16 08:53:47 -07:00
Eddie Hung	ba8ccbdea8	Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix ... abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box	2019-07-16 08:52:14 -07:00
Miodrag Milanovic	2b469e82a7	Fix check logic in extract_fa	2019-07-16 10:35:18 +02:00
Eddie Hung	5f00d335d4	Oops forgot these files	2019-07-15 15:03:15 -07:00
Eddie Hung	dd59375a66	Add xilinx_dsp for register packing	2019-07-15 14:46:31 -07:00
Clifford Wolf	2a7198db51	Merge pull request #1189 from YosysHQ/eddie/fix1151 ... Error out if enable > dbits in memory_bram file	2019-07-15 20:06:35 +02:00
Clifford Wolf	2c5c53e4c1	Merge pull request #1190 from YosysHQ/eddie/fix_1099 ... extract_fa to return nothing more gracefully	2019-07-15 20:05:56 +02:00
whitequark	2de7e92bb8	opt_lut: make less chatty.	2019-07-13 16:49:56 +00:00
Eddie Hung	9b91d815b5	If ConstEval fails do not log_abort() but return gracefully	2019-07-13 04:13:57 -07:00
Eddie Hung	ab3917d079	Error out if enable > dbits	2019-07-13 03:39:23 -07:00
Eddie Hung	fb062c3426	Add comment	2019-07-13 00:52:21 -07:00
Eddie Hung	e9bdc86c0e	duplicate -> clone	2019-07-12 19:33:02 -07:00
Eddie Hung	be0cb7f4b8	More cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	7d583f9e57	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	83f23a24a8	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	1adbfb5533	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	39a7c7c54c	More cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	91c07be196	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	399e1ec870	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	58dbb28fd3	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	7dc15bdd2d	Do not double count cells in abc	2019-07-12 08:22:26 -07:00
Eddie Hung	237d8651a5	Error out if abc9 not called with -lut or -luts	2019-07-11 09:58:00 -07:00
Eddie Hung	0c3ed73dad	Count $_NOT_ cells turned into $luts	2019-07-11 09:55:14 -07:00
Eddie Hung	33862d0445	WIP for fixing partitioning, temporarily do not partition	2019-07-11 09:22:52 -07:00
Eddie Hung	c0abd18799	Enable &mfs for abc9, even if it only currently works for ice40	2019-07-11 08:49:06 -07:00
Clifford Wolf	fd3d5cefad	Merge pull request #1179 from whitequark/attrmap-proc ... attrmap: also consider process, switch and case attributes	2019-07-11 07:23:28 +02:00
Eddie Hung	9f608d6be3	write_verilog with *.v extension	2019-07-10 20:25:59 -07:00
Eddie Hung	71acd3ddcf	Remove -retime from abc9, revert to abc behav with separate clock/en domains	2019-07-10 18:57:44 -07:00
Eddie Hung	052060f109	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-07-10 16:05:41 -07:00
whitequark	ea447220da	attrmap: also consider process, switch and case attributes.	2019-07-10 12:30:53 +00:00
Clifford Wolf	c66b4b9131	Merge pull request #1177 from YosysHQ/clifford/async ... Fix clk2fflogic adff reset semantic to negative hold time on reset	2019-07-10 08:48:20 +02:00