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More cleanup

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This commit is contained in:
Eddie Hung 2019-07-12 19:21:03 -07:00
parent 7d583f9e57
commit be0cb7f4b8
1 changed files with 2 additions and 8 deletions
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10
passes/techmap/abc9.cc
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@ -30,8 +30,7 @@
"&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
"&mfs; &ps -l"
#else
#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs -b; &ps -l"
//#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &put -v; dch -f; if {W} {D} -vo; mfs2; &get -vm; &ps -l"
#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
#endif
@ -756,16 +755,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::SigBit a_bit = not_cell->getPort("\\A");
RTLIL::SigBit y_bit = not_cell->getPort("\\Y");
RTLIL::Const driver_mask;
RTLIL::Wire *orig_a_bit_wire = a_bit.wire;
decltype(bit2sinks)::const_iterator jt;
a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
y_bit.wire = module->wires_.at(remap_name(y_bit.wire->name));
if (orig_a_bit_wire->port_output)
goto duplicate_lut;
jt = bit2sinks.find(a_bit);
auto jt = bit2sinks.find(a_bit);
if (jt == bit2sinks.end())
goto duplicate_lut;