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Merge pull request #1177 from YosysHQ/clifford/async

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Fix clk2fflogic adff reset semantic to negative hold time on reset
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Clifford Wolf 2019-07-10 08:48:20 +02:00 • committed by GitHub
commit c66b4b9131
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5 changed files with 135 additions and 8 deletions
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7
passes/sat/clk2fflogic.cc
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@ -253,6 +253,13 @@ struct Clk2fflogicPass : public Pass {
SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
Const rstval = cell->parameters["\\ARST_VALUE"];
Wire *past_arst = module->addWire(NEW_ID);
module->addFf(NEW_ID, arst, past_arst);
if (cell->parameters["\\ARST_POLARITY"].as_bool())
arst = module->LogicOr(NEW_ID, arst, past_arst);
else
arst = module->LogicAnd(NEW_ID, arst, past_arst);
if (cell->parameters["\\ARST_POLARITY"].as_bool())
module->addMux(NEW_ID, qval, rstval, arst, sig_q);
else