1110 commits

Author	SHA1	Message	Date
Clifford Wolf	a3a13cce32	Fixed detection of "task foo(bar);" syntax error	2015-09-22 21:34:21 +02:00
Clifford Wolf	6176f4d081	Fixed multi-level prefix resolving	2015-09-22 20:52:02 +02:00
Clifford Wolf	4b8200eb49	Fixed segfault on invalid verilog constant 1'b_	2015-09-22 08:13:09 +02:00
Andrew Zonenberg	c469f22144	Improvements to $display system task	2015-09-19 10:33:37 +02:00
Clifford Wolf	9db05d17fe	Added AST_INITIAL checks for $finish and $display	2015-09-18 09:50:57 +02:00
Andrew Zonenberg	7141f65533	Initial implementation of $display()	2015-09-18 09:36:46 +02:00
Andrew Zonenberg	e446e651cb	Initial implementation of $finish()	2015-09-18 09:30:25 +02:00
Clifford Wolf	b10ea0550d	gcc-4.6 build fixes	2015-09-01 12:51:23 +02:00
Clifford Wolf	eb38722e98	Fixed handling of memory read without address	2015-08-22 14:46:42 +02:00
Clifford Wolf	a7ab9172f9	Small corrections to const2ast warning messages	2015-08-17 16:22:53 +02:00
Florian Zeitz	0491042849	Check base-n literals only contain valid digits	2015-08-17 15:37:33 +02:00
Florian Zeitz	64ccbf8510	Warn on literals exceeding the specified bit width	2015-08-17 15:27:35 +02:00
Larry Doolittle	6c00704a5e	Another block of spelling fixes ... Smaller this time	2015-08-14 23:27:05 +02:00
Larry Doolittle	022f570563	Keep gcc from complaining about uninitialized variables	2015-08-14 23:26:49 +02:00
Clifford Wolf	0350074819	Re-created command-reference-manual.tex, copied some doc fixes to online help	2015-08-14 11:27:19 +02:00
Clifford Wolf	84bf862f7c	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00
Clifford Wolf	e4ef000b70	Adjust makefiles to work with out-of-tree builds ... This is based on work done by Larry Doolittle	2015-08-12 15:04:44 +02:00
Clifford Wolf	45ee2ba3b8	Fixed handling of [a-fxz?] in decimal constants	2015-08-11 11:32:37 +02:00
Marcus Comstedt	c836faae3e	Add -noautowire option to verilog frontend	2015-08-01 12:16:54 +02:00
Clifford Wolf	8d6d5c30d9	Added WORDS parameter to $meminit	2015-07-31 10:40:09 +02:00
Clifford Wolf	4513ff1b85	Fixed nested mem2reg	2015-07-29 16:37:08 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	13983e8318	Fixed handling of parameters with reversed range	2015-06-08 14:03:06 +02:00
Clifford Wolf	99b8746d27	Fixed signedness of genvar expressions	2015-05-29 20:08:00 +02:00
Clifford Wolf	08a4af3cde	Improvements in BLIF front-end	2015-05-24 08:03:21 +02:00
Clifford Wolf	6061b7bd58	bugfix in blif front-end	2015-05-18 11:15:49 +02:00
Clifford Wolf	3ecb2bf067	Improved .latch support in BLIF front-end	2015-05-17 18:58:24 +02:00
Clifford Wolf	2cc4e75914	Added read_blif command	2015-05-17 15:25:03 +02:00
Clifford Wolf	e5116eeb77	Generalized blifparse API	2015-05-17 15:10:37 +02:00
Clifford Wolf	7dad017c9c	abc/blifparse files reorganization	2015-05-17 14:44:28 +02:00
Clifford Wolf	61512b6f41	Verific build fixes	2015-05-17 08:19:52 +02:00
Clifford Wolf	7ff802e199	Verilog front-end: define `BLACKBOX in -lib mode	2015-04-19 21:30:46 +02:00
Clifford Wolf	a923a63a89	Ignore celldefine directive in verilog front-end	2015-03-25 19:46:12 +01:00
Clifford Wolf	422794c584	Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()	2015-03-01 11:20:22 +01:00
Clifford Wolf	1f1deda888	Added non-std verilog assume() statement	2015-02-26 18:47:39 +01:00
Clifford Wolf	d5ce9a32ef	Added deep recursion warning to AST simplify	2015-02-20 10:33:20 +01:00
Clifford Wolf	dc1a0f06fc	Parser support for complex delay expressions	2015-02-20 10:21:36 +01:00
Clifford Wolf	e0e6d130cd	YosysJS stuff	2015-02-19 13:36:54 +01:00
Clifford Wolf	c2ba4fb2fd	Convert floating point cell parameters to strings	2015-02-18 23:35:23 +01:00
Clifford Wolf	e9368a1d7e	Various fixes for memories with offsets	2015-02-14 14:21:15 +01:00
Clifford Wolf	7f1a1759d7	Added "read_verilog -nomeminit" and "nomeminit" attribute	2015-02-14 11:21:12 +01:00
Clifford Wolf	a8e9d37c14	Creating $meminit cells in verilog front-end	2015-02-14 10:49:30 +01:00
Clifford Wolf	ef151b0b30	Fixed handling of "//" in filenames in verilog pre-processor	2015-02-14 08:41:03 +01:00
Clifford Wolf	cd919abdf1	Added AstNode::simplify() recursion counter	2015-02-13 12:33:12 +01:00
Clifford Wolf	4f68a77e3f	Improved read_verilog support for empty behavioral statements	2015-02-10 12:17:29 +01:00
Clifford Wolf	234a45a3d5	Ignore explicit assignments to constants in HDL code	2015-02-08 00:58:03 +01:00
Clifford Wolf	c8305e3a6d	Fixed a bug with autowire bit size ... (removed leftover from when we tried to auto-size the wires)	2015-02-08 00:48:23 +01:00
Clifford Wolf	2a9ad48eb6	Added ENABLE_NDEBUG makefile options	2015-01-24 12:16:46 +01:00
Clifford Wolf	df9d096a7d	Ignoring more system task and functions	2015-01-15 13:08:19 +01:00
Clifford Wolf	a588a4a5c9	Fixed handling of "input foo; reg [0:0] foo;"	2015-01-15 12:53:12 +01:00