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									 Clifford Wolf | 4f0d4899ce | Added support for $stop system task | 2016-03-21 16:19:51 +01:00 |  | 
				
					
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									 Clifford Wolf | e5d42ebb4d | Added $display %m support, fixed mem leak in $display, fixes #128 | 2016-03-19 11:51:13 +01:00 |  | 
				
					
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									 Clifford Wolf | ef4207d5ad | Fixed localparam signdness, fixes #127 | 2016-03-18 12:15:00 +01:00 |  | 
				
					
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									 Clifford Wolf | b6d08f39ba | Set "nosync" attribute on internal task/function wires | 2016-03-18 10:53:29 +01:00 |  | 
				
					
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									 Clifford Wolf | 33c10350b2 | Fixed Verilog parser fix and more similar improvements | 2016-03-15 12:22:31 +01:00 |  | 
				
					
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									 Andrew Becker | 81d4e9e7c1 | Use left-recursive rule for cell_port_list in Verilog parser. | 2016-03-15 12:03:40 +01:00 |  | 
				
					
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									 Clifford Wolf | 35a6ad4cc1 | Fixed typos in verilog_defaults help message | 2016-03-10 11:14:51 +01:00 |  | 
				
					
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									 Clifford Wolf | 22c549ab37 | Fixed BLIF parser for empty port assignments | 2016-02-24 09:16:43 +01:00 |  | 
				
					
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									 Clifford Wolf | bcc873b805 | Fixed some visual studio warnings | 2016-02-13 17:31:24 +01:00 |  | 
				
					
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									 Clifford Wolf | 7bd329afa0 | Support for more Verific primitives (patch I got per email) | 2016-02-13 08:19:30 +01:00 |  | 
				
					
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									 Clifford Wolf | 6a27cbe5b1 | Bugfix in Verific front-end | 2016-02-03 08:59:57 +01:00 |  | 
				
					
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									 Clifford Wolf | 4a3e1ded1e | Updated verific build instructions | 2016-02-02 19:50:17 +01:00 |  | 
				
					
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									 Clifford Wolf | ba407da187 | Added addBufGate module method | 2016-02-02 11:26:07 +01:00 |  | 
				
					
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									 Rick Altherr | 34969d4140 | genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree() | 2016-01-31 09:20:16 -08:00 |  | 
				
					
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									 Clifford Wolf | 5e90a78466 | Various improvements in BLIF front-end | 2015-12-20 13:12:24 +01:00 |  | 
				
					
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									 Clifford Wolf | 4a697accd4 | Fixed oom bug in ilang parser | 2015-11-29 20:30:32 +01:00 |  | 
				
					
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									 Clifford Wolf | 32f5ee117c | Fixed performance bug in ilang parser | 2015-11-27 19:46:47 +01:00 |  | 
				
					
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									 Clifford Wolf | ab2d8e5c8c | Added PRIM_DLATCHRS support to verific front-end | 2015-11-24 12:16:19 +01:00 |  | 
				
					
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									 Clifford Wolf | c86fbae3d1 | Fixed handling of re-declarations of wires in tasks and functions | 2015-11-23 17:09:57 +01:00 |  | 
				
					
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									 Clifford Wolf | 415e0a1b90 | Fixed performance bug in Verific importer | 2015-11-16 12:38:56 +01:00 |  | 
				
					
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									 Clifford Wolf | b18f3a2974 | Changes for Verific 3.16_484_32_151112 | 2015-11-12 19:28:14 +01:00 |  | 
				
					
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									 Clifford Wolf | 7ae3d1b5a9 | More bugfixes in handling of parameters in tasks and functions | 2015-11-12 13:02:36 +01:00 |  | 
				
					
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									 Clifford Wolf | 34f2b84fb6 | Fixed handling of parameters and localparams in functions | 2015-11-11 10:54:35 +01:00 |  | 
				
					
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									 Clifford Wolf | 207736b4ee | Import more std:: stuff into Yosys namespace | 2015-10-25 19:30:49 +01:00 |  | 
				
					
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									 Clifford Wolf | 5308c1e02a | Fixed bug in verilog parser | 2015-10-15 15:19:23 +02:00 |  | 
				
					
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									 Clifford Wolf | f13e387321 | SystemVerilog also has assume(), added implicit -D FORMAL | 2015-10-13 14:21:20 +02:00 |  | 
				
					
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									 Clifford Wolf | ba4cce9f19 | Added support for "parameter" and "localparam" in global context | 2015-10-07 14:59:08 +02:00 |  | 
				
					
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									 Clifford Wolf | e51dcc83d0 | Fixed complexity of assigning to vectors in constant functions | 2015-10-01 12:15:35 +02:00 |  | 
				
					
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									 Clifford Wolf | 9caeadf797 | Fixed detection of unconditional $readmem[hb] | 2015-09-30 15:46:51 +02:00 |  | 
				
					
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									 Clifford Wolf | f9d7df0869 | Bugfixes in $readmem[hb] | 2015-09-25 13:49:48 +02:00 |  | 
				
					
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									 Clifford Wolf | b2544cfcf7 | Fixed segfault in AstNode::asReal | 2015-09-25 12:38:01 +02:00 |  | 
				
					
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									 Clifford Wolf | 924d9d6e86 | Added read-enable to memory model | 2015-09-25 12:23:11 +02:00 |  | 
				
					
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									 Clifford Wolf | 1b8cb9940e | Fixed AstNode::mkconst_bits() segfault on zero-sized constant | 2015-09-24 11:21:20 +02:00 |  | 
				
					
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									 Clifford Wolf | e2e092b144 | Added read_verilog -nodpi | 2015-09-23 08:23:38 +02:00 |  | 
				
					
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									 Clifford Wolf | 089c1e176f | Bugfix in handling of multi-dimensional memories | 2015-09-23 07:56:17 +02:00 |  | 
				
					
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									 Clifford Wolf | 559929e341 | Warning for $display/$write outside initial block | 2015-09-23 07:16:03 +02:00 |  | 
				
					
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									 Clifford Wolf | b845b77f86 | Fixed support for $write system task | 2015-09-23 07:10:56 +02:00 |  | 
				
					
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									 Clifford Wolf | a3a13cce32 | Fixed detection of "task foo(bar);" syntax error | 2015-09-22 21:34:21 +02:00 |  | 
				
					
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									 Clifford Wolf | 6176f4d081 | Fixed multi-level prefix resolving | 2015-09-22 20:52:02 +02:00 |  | 
				
					
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									 Clifford Wolf | 4b8200eb49 | Fixed segfault on invalid verilog constant 1'b_ | 2015-09-22 08:13:09 +02:00 |  | 
				
					
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									 Andrew Zonenberg | c469f22144 | Improvements to $display system task | 2015-09-19 10:33:37 +02:00 |  | 
				
					
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									 Clifford Wolf | 9db05d17fe | Added AST_INITIAL checks for $finish and $display | 2015-09-18 09:50:57 +02:00 |  | 
				
					
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									 Andrew Zonenberg | 7141f65533 | Initial implementation of $display() | 2015-09-18 09:36:46 +02:00 |  | 
				
					
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									 Andrew Zonenberg | e446e651cb | Initial implementation of $finish() | 2015-09-18 09:30:25 +02:00 |  | 
				
					
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									 Clifford Wolf | b10ea0550d | gcc-4.6 build fixes | 2015-09-01 12:51:23 +02:00 |  | 
				
					
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									 Clifford Wolf | eb38722e98 | Fixed handling of memory read without address | 2015-08-22 14:46:42 +02:00 |  | 
				
					
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									 Clifford Wolf | a7ab9172f9 | Small corrections to const2ast warning messages | 2015-08-17 16:22:53 +02:00 |  | 
				
					
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									 Florian Zeitz | 0491042849 | Check base-n literals only contain valid digits | 2015-08-17 15:37:33 +02:00 |  | 
				
					
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									 Florian Zeitz | 64ccbf8510 | Warn on literals exceeding the specified bit width | 2015-08-17 15:27:35 +02:00 |  | 
				
					
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									 Larry Doolittle | 6c00704a5e | Another block of spelling fixes Smaller this time | 2015-08-14 23:27:05 +02:00 |  |