853 commits

Author	SHA1	Message	Date
Clifford Wolf	68a829dbcd	Merge branch 'master' of github.com:cliffordwolf/yosys	2018-02-16 14:22:11 +01:00
Clifford Wolf	2c95dfcb5b	Improve handling of "bus" pins in liberty front-end (some files use bus.pin.direction) ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-15 17:36:08 +01:00
Clifford Wolf	bc8ab3ab44	Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF	2018-02-15 15:26:37 +01:00
Clifford Wolf	6c00e064e2	Fix single-bit $stable handling in verific front-end ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-01 12:51:49 +01:00
Clifford Wolf	9af40faa0b	Add Verific attribute handling for assert/assume/cover/live/fair cells ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-01-31 19:06:51 +01:00
Clifford Wolf	675f53abbb	Fix permissions on verific vdb files	2018-01-28 18:52:01 +01:00
Clifford Wolf	1d8161b432	Fixed handling of synchronous and asynchronous assertion/assumption/cover in verific bindings ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-01-23 17:42:40 +01:00
Clifford Wolf	a96c775a73	Add support for "yosys -E" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-01-07 16:36:13 +01:00
Clifford Wolf	26c4323d48	Merge pull request #479 from Fatsie/latch_without_data ... Some standard cell libraries include a latch with only set/reset.	2018-01-05 23:00:28 +01:00
Clifford Wolf	c80315cea4	Bugfix in hierarchy handling of blackbox module ports ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-01-05 13:28:45 +01:00
Staf Verhaegen	5126c6f22b	Some standard cell libraries include a latch with only set/reset.	2018-01-03 21:36:02 +00:00
Clifford Wolf	34005348b6	Bugfix in verilog_defaults argument parser	2017-12-24 17:21:37 +01:00
Clifford Wolf	ba90e08398	Add support for Verific PRIM_SVA_NOT properties	2017-12-10 01:10:03 +01:00
Clifford Wolf	e4a4c0e10c	Add Verific OPER_SVA_STABLE support	2017-12-10 00:59:44 +01:00
Clifford Wolf	27916105a9	Refactoring Verific SVA rewriter	2017-12-10 00:26:26 +01:00
Clifford Wolf	8364f509e3	Fix error handling for nested always/initial	2017-12-02 18:52:05 +01:00
Clifford Wolf	777f2881d8	Add Verilog "automatic" keyword (ignored in synthesis)	2017-11-23 08:51:38 +01:00
Clifford Wolf	5b6e52118c	Accept real-valued delay values	2017-11-18 10:01:30 +01:00
William D. Jones	abc5b4b8ce	Accommodate Windows-style paths during include-file processing.	2017-11-14 16:16:24 -05:00
Clifford Wolf	a8cf431d9c	Remove vhdl2verilog	2017-10-25 14:50:22 +02:00
Clifford Wolf	0a31a0b3ae	Remove all PSL support code from verific.cc	2017-10-20 13:14:04 +02:00
Clifford Wolf	1954c78ea7	Add "verific -vlog-libdir"	2017-10-13 20:23:19 +02:00
Clifford Wolf	e7a3c47cc7	Add "verific -vlog-incdir" and "verific -vlog-define"	2017-10-13 20:12:51 +02:00
Clifford Wolf	05068af880	Update Verific README	2017-10-13 17:11:53 +02:00
Clifford Wolf	bc5cc4e103	Add Verific fairness/liveness support	2017-10-12 12:00:09 +02:00
Clifford Wolf	12c10892e6	Merge branch 'master' of github.com:cliffordwolf/yosys	2017-10-10 15:16:45 +02:00
Clifford Wolf	c10e96c9ec	Start work on pre-processor for Verific SVA properties	2017-10-10 15:16:39 +02:00
Clifford Wolf	bc80426d45	Remove some dead code	2017-10-10 12:00:48 +02:00
Clifford Wolf	caa78388cd	Allow $past, $stable, $rose, $fell in $global_clock blocks	2017-10-10 11:59:32 +02:00
Clifford Wolf	fc3378916d	Improve handling of Verific errors	2017-10-05 14:38:32 +02:00
Clifford Wolf	ee56a887b6	Improve Verific error handling, check VHDL static asserts	2017-10-04 18:56:28 +02:00
Clifford Wolf	b92ff2706e	Fix nasty bug in Verific bindings	2017-10-04 17:23:42 +02:00
Clifford Wolf	a381188b92	Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys	2017-10-03 18:23:45 +02:00
Udi Finkelstein	eb40278a16	Turned a few member functions into const, esp. dumpAst(), dumpVlog().	2017-09-30 07:37:38 +03:00
Udi Finkelstein	72a08eca3d	Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution ... (Oreilly 'Flex & Bison' page 189)	2017-09-30 06:39:07 +03:00
Clifford Wolf	dbfd8460a9	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
Udi Finkelstein	e951ac0dfb	$size() now works correctly for all cases! ... It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.	2017-09-26 20:34:24 +03:00
Udi Finkelstein	6ddc6a7af4	$size() seems to work now with or without the optional parameter. ... Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.	2017-09-26 19:18:25 +03:00
Udi Finkelstein	7e391ba904	enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog	2017-09-26 09:19:56 +03:00
Udi Finkelstein	2dea42e903	Added $bits() for memories as well.	2017-09-26 09:11:25 +03:00
Udi Finkelstein	17f8b41605	$size() now works with memories as well!	2017-09-26 08:36:45 +03:00
Udi Finkelstein	64eb8f29ad	Add $size() function. At the moment it works only on expressions, not on memories.	2017-09-26 06:25:42 +03:00
Clifford Wolf	30396270a2	Increase maximum LUT size in blifparse to 12 bits	2017-09-27 15:27:42 +02:00
Clifford Wolf	91d9c50bb3	Parse reals as string in JSON front-end	2017-09-26 14:37:03 +02:00
Clifford Wolf	2c04d883b1	Minor coding style fix	2017-09-26 13:50:14 +02:00
Clifford Wolf	cb1d439d10	Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master	2017-09-26 13:48:13 +02:00
Clifford Wolf	2cc09161ff	Fix ignoring of simulation timings so that invalid module parameters cause syntax errors	2017-09-26 01:52:59 +02:00
combinatorylogic	64ca0be971	Adding support for string macros and macros with arguments after include	2017-09-21 18:25:02 +01:00
Robert Ou	366ce87cff	json: Parse inout correctly rather than as an output	2017-08-14 12:09:03 -07:00
Clifford Wolf	15073790bf	Add merging of "past FFs" to verific importer	2017-07-29 00:10:38 +02:00