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Akash Levy
8962c232ab
Merge pull request #205 from Silimate/akashlevy/opt_prienc-consteval-cut
opt_prienc: require ConstEval fingerprint inputs to be a valid cut
2026-07-07 00:28:38 -07:00
Akash Levy
0a69890e3f opt_prienc: require ConstEval fingerprint inputs to be a valid cut
The round-robin (and PE/CLZ/CTZ) fingerprints pin candidate request/
start/select signals as free ConstEval inputs and evaluate the encoder
output cone. ConstEval::eval() re-computes and re-set()s the FULL output
of every combinational cell it needs. If a pinned bit is a combinational
cell output and a sibling output bit of that same cell is pulled into the
cone, evaluating the sibling re-sets the pinned bit to the cell's real
value, contradicting the free value we pinned and tripping the assertion
`current_val[i].wire != NULL || current_val[i] == value[i]` in
kernel/consteval.h.

The earlier clean_set_signals() guard only rejected constant/aliased
bits; it did not ensure the pinned signals form a valid cut. Candidates
are gathered purely by width, so an internal combinational wire (e.g. a
slice of a wider arithmetic result) can be pinned, which is exactly what
crashed on veer_speed1/picorv32/murax/raygentop.

Add is_valid_consteval_cut(): a pinned bit is a safe leaf when it is a
primary input, sequential-cell output or undriven (absent from
bit_to_driver, which holds combinational drivers only); a combinational
output is safe only if that cell's entire output lies within the pinned
cut. Apply it in both fingerprint() and fingerprint_rr(). Declining an
unclean cut only forgoes a possible rewrite, never yields a wrong one,
and the intended arbiter inputs (request ports, idx_last flop outputs)
remain valid cuts so real round-robin patterns still rewrite.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-07 00:00:24 -07:00
Akash Levy
a4fa9c31e8
Merge pull request #204 from Silimate/akashlevy/opt_prienc-consteval-fix
opt_prienc: fix ConstEval crash on constant/aliased fingerprint inputs
2026-07-06 22:23:04 -07:00
Akash Levy
945e4a403b tests/opt: add generalization coverage for the QoR pattern passes
Prove the three pattern detectors work on unseen inputs, not just the RTL
they were derived from. Because detection is functional (ConstEval
fingerprinting over the reachable input space), correctness is established
per case with equiv_opt -assert (full) or a SAT miter clamped to the
reachable range (non-power-of-two), and detection is confirmed with a
w:*tag* probe.

opt_priokey:
  D1-D3  spelling variants (explicit shift-or set, compound derived guard,
         accumulator also exported) -- all fire and prove equivalent.
  E1-E2  parameter sweep P=2..8, S=4..32.
  E3     non-power-of-two S=12 reachable-range equivalence via SAT miter.
  E4     same shape under -strict declines to rewrite (formal-flow safety).
  F1-F2  near-miss negatives (clear accumulator, multi-hot set) -> no rewrite.

opt_prienc (round-robin):
  RR4-RR5 DEPTH sweep 8/32, full sequential equivalence.
  RR6     non-power-of-two DEPTH=7 reachable-range equivalence (SAT miter).
  RR7     an entirely different spelling (upward wrap-scan, first-hit) of the
          same arbiter -- fires and proves equivalent.
  RR8     fixed-priority (no rotating pointer) negative.

opt_first_fit_alloc (coalesce):
  H1      inline same-category compare (no precomputed matrix) spelling.
  H2      different slot/field shape (N=8, NB=8, W=3).

All new cases pass locally; they avoid brittle exact cell-count asserts so
they are robust to upstream optimization drift.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 22:05:50 -07:00
Akash Levy
676ac184ed opt_prienc: guard ConstEval fingerprint inputs against constant/aliased bits
The round-robin detector fed sigmap(wire) signals straight into
ConstEval::set() while sweeping test vectors. On real designs a candidate
bus can have bits tied to constants, repeated bits, or a req/start pair
that alias to the same net after sigmap. ConstEval::set() asserts
(current_val[i].wire != NULL || current_val[i] == value[i]) when asked to
re-pin such a bit to a conflicting value, crashing the pass
(consteval.h:83) on designs like veer/picorv32/murax/raygentop under
formal synthesis.

Add clean_set_signals() and reject any fingerprint candidate whose
set-signals contain constant bits, repeated bits, or overlap each other,
in both the priority-encoder and round-robin paths. Skipping an unclean
candidate only forgoes a possible rewrite; it never produces an incorrect
one. Clean candidates (the intended patterns) are unaffected.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 21:35:51 -07:00
Akash Levy
84f4054584
Merge pull request #203 from Silimate/frontend-verific
bump verific
2026-07-06 20:33:46 -07:00
Stan Lee
189d177478 bump verific 2026-07-06 16:18:47 -07:00
Akash Levy
087f5bd254
Merge pull request #202 from Silimate/akashlevy/qor-pattern-passes
opt: recognize three QoR logic-depth patterns
2026-07-06 13:56:29 -07:00
Akash Levy
f5c54e5905 opt_prienc: give each round-robin req candidate its own fingerprint budget
The max_pairs budget was a single running counter shared across all
req_wire iterations, so once a start-candidate-heavy first req size
exhausted it, every later req size broke on its first start candidate and
was silently skipped. Reset the budget per req_wire so all req sizes get
a fair chance. (Completeness only; fingerprint_rr still validates every
match, so this never affected correctness.)

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 13:28:54 -07:00
Akash Levy
0dd22db85b
Merge pull request #199 from Silimate/carvenetlist
Pass carvenetlist
2026-07-06 13:25:06 -07:00
Akash Levy
00e48706df opt: recognize three QoR logic-depth patterns
Extend two existing opt passes and add one new pass to collapse
serial/dynamic-index structures that were leaving high logic depth:

- opt_first_fit_alloc: recognize the "coalesce-matrix" first-fit
  allocator variant (same_cat[i][k] coalescing gated on the leader's
  enable, driven from a raw input enable). Rewrite both the lane_slot
  allocation and the xbar field gather from one shared log-depth scan.

- opt_prienc: detect round-robin / rotated-priority scans (req scanned
  from idx_last downward with wraparound) and rewrite the depth-N
  idx--/req[idx] mux chain to rotate -> log-depth priority-encode ->
  unrotate.

- opt_priokey (new): recognize priority-by-key one-hot accumulators and
  replace each dynamic taken[key] read ($shiftx/$bmux) with the
  equivalent pairwise-key-compare reduction, dropping the wide dynamic
  indexing. Supports -strict for full-key-range formal validation.

Each includes self-contained tests (equiv_opt / sat -prove-asserts,
mux-bound and negative cases) in tests/opt/.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 12:56:38 -07:00
Akash Levy
80bc373519 carvenetlist: keep cone boundary gate; address review comments
Fix the failing regression test: the single-fanout passthrough removal was
shorting out a cone's only real gate (e.g. a lone $_NOT_ driving an output),
replacing it with a bare wire. That drops the gate entirely (nothing left to
characterize) and, for an inverter, silently drops the inversion, making the
carved cell inequivalent to the RTL. Only short a redundant re-driver whose
input is driven by another in-cone cell; keep a passthrough that reads a
primary input (the cell-under-test's boundary gate).

Also address Greptile review comments:
- fix swapped log_warning arguments in the split-boundary-port diagnostic.
- error out (instead of silently overwriting) when two cell groups rename to
  the same carved module name (e.g. slow_<enc> and fast_<enc> -> <enc>).
- derive pq_speed from the explicit "fast_" base prefix.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 09:13:18 -07:00
Akash Levy
a436888326 Merge branch 'main' into carvenetlist 2026-07-06 08:38:27 -07:00
Akash Levy
25f4376018 Merge remote-tracking branch 'upstream/main' 2026-07-06 08:37:44 -07:00
Akash Levy
19c28d0e00 Merge branch 'main' into carvenetlist 2026-07-06 08:37:13 -07:00
Akash Levy
63dd7b7ee9
Merge pull request #201 from Silimate/merge5
Merge from upstream
2026-07-06 08:30:57 -07:00
Akash Levy
fc94513584
Merge pull request #200 from Silimate/opt_cut_region_speedup
Speed up opt_* using cut_region with shared_ce
2026-07-06 08:10:04 -07:00
Akash Levy
a2e38e2022 Merge from upstream 2026-07-06 07:47:32 -07:00
Akash Levy
3aa52fb1e5 Pass carvenetlist 2026-07-06 07:44:01 -07:00
Akash Levy
bab0ee6bf8 Speed up opt_* using cut_region with shared_ce 2026-07-06 07:42:47 -07:00
Akash Levy
9d39a82587 Allow sim pass to handle 4-input gates 2026-07-06 07:41:08 -07:00
Akash Levy
b600028644 Reduce verbosity of opt_dff 2026-07-06 07:40:47 -07:00
Akash Levy
b609976d7d Add some cpp stuff 2026-07-06 07:40:22 -07:00
Akash Levy
7166468c55 Naming improvements 2026-07-06 07:40:14 -07:00
nella
006cbc8f72
Merge pull request #5842 from YosysHQ/nella/opt_dff_elim_improvements
opt_dff: Eliminate equivalent bits
2026-07-06 12:02:50 +00:00
nella
0e56ca02ed Make opt_dff -sat conflict with -keepdc. 2026-07-06 13:47:10 +02:00
Akash Levy
d578dafc82
Merge pull request #198 from Silimate/ci_tweaks
ci: cache build instead of using artifacts
2026-07-03 13:47:32 -07:00
Mohamed Gaber
56dd057ab4
test/ci fixes
- fix incorrect repo_url output
- fix parsing in test_splitnets to match new format
- fix silimate-shell.nix referring to removed derivation
2026-07-02 18:56:25 +03:00
Miodrag Milanović
b285b72e36
Merge pull request #5999 from YosysHQ/update_abc
Update ABC as per 2026-07-02
2026-07-02 10:00:45 +00:00
Miodrag Milanovic
30a813b090 Update ABC as per 2026-07-02 2026-07-02 11:34:22 +02:00
Mohamed Gaber
268ff49030
ci: target different repo for release 2026-07-02 09:30:59 +03:00
Mohamed Gaber
4a245f9fed
ci: cache build instead of using artifacts 2026-06-30 13:34:25 +03:00
Miodrag Milanović
afe6b18f28
Merge pull request #5995 from YosysHQ/log_cleanup
Removed rewrite leftovers from log
2026-06-29 07:44:40 +00:00
Miodrag Milanovic
97e2600e5c Removed rewrite leftovers from log 2026-06-29 08:32:44 +02:00
Akash Levy
f7dc45a478 More verbosity in Module::add failure due to duplicate 2026-06-28 20:29:09 -07:00
Akash Levy
77cd9e1edc stat bugfix 2026-06-28 20:28:23 -07:00
Akash Levy
d0380bf8f0 New stat 2026-06-28 01:18:21 -07:00
Akash Levy
2f5dfa8fd9
Merge pull request #196 from Silimate/merge4
Merge4
2026-06-26 12:15:20 -07:00
Miodrag Milanović
e74db6deac
Merge pull request #5994 from YosysHQ/manual_brew
Install just some brew packages
2026-06-26 19:14:38 +00:00
Miodrag Milanovic
0c0d3f717c Install just some brew packages 2026-06-26 20:57:24 +02:00
Akash Levy
04a604f9fe Smallfix to simplemap 2026-06-26 11:41:04 -07:00
Miodrag Milanović
7c5d9a37bf
Merge pull request #5993 from YosysHQ/nix
Moving nix to weekly as non-critical
2026-06-26 17:52:56 +00:00
Miodrag Milanovic
9144d2bd2f Moving nix to weekly as non-critical 2026-06-26 19:35:44 +02:00
Akash Levy
da7a6b8331 Merge remote-tracking branch 'upstream' 2026-06-26 09:43:12 -07:00
Miodrag Milanović
195593f2b0
Merge pull request #5991 from YosysHQ/test_build
Fix skipping test-build on merge
2026-06-26 16:26:22 +00:00
Miodrag Milanovic
049dca7ded Fix skipping test-build on merge 2026-06-26 18:02:37 +02:00
Miodrag Milanović
f624bcf2db
Merge pull request #5990 from YosysHQ/self_sanitizer
Self hosted sanitizer
2026-06-26 15:39:54 +00:00
Miodrag Milanovic
cd4198e024 Skip this step during merge queue since we have already run those 2026-06-26 17:17:35 +02:00
Miodrag Milanovic
0c13257915 Sanitizer self hosted 2026-06-26 17:10:44 +02:00
Miodrag Milanović
6cee0af8ad
Merge pull request #5989 from YosysHQ/ccache2
Store caches on main
2026-06-26 13:15:55 +00:00