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More verbosity in Module::add failure due to duplicate

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This commit is contained in:
Akash Levy 2026-06-28 20:29:09 -07:00
parent 77cd9e1edc
commit f7dc45a478
1 changed files with 3 additions and 0 deletions
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3
kernel/rtlil.cc
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@ -2895,6 +2895,9 @@ std::vector<RTLIL::NamedObject*> RTLIL::Module::selected_members() const
void RTLIL::Module::add(RTLIL::Wire *wire)
{
log_assert(!wire->name.empty());
if (count_id(wire->name) != 0)
log_error("RTLIL::Module::add: duplicate name '%s' in module '%s' (already used by an "
"existing wire/cell/memory/process).\n", log_id(wire->name), log_id(name));
log_assert(count_id(wire->name) == 0);
log_assert(refcount_wires_ == 0);
wires_[wire->name] = wire;