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Author	SHA1	Message	Date
Clifford Wolf	42a971226b	Fixed default build config	2016-08-16 22:44:38 +02:00
Clifford Wolf	1419f3983e	Merge pull request #203 from cr1901/master ... Add MSYS2-compatible build.	2016-08-16 22:41:53 +02:00
William D. Jones	5299b17056	Add MSYS2-compatible build.	2016-08-16 14:41:59 -04:00
Clifford Wolf	5767e4bc4d	Use _Exit(0) on win32, always use _Exit(1) in log_error()	2016-08-16 09:38:54 +02:00
Clifford Wolf	5531bd7578	Updated ABC to hg rev a86455b00da5	2016-08-16 09:08:26 +02:00
Clifford Wolf	00f29d5e5c	Fixed use-after-free dict<> usage pattern in hierarchy.cc	2016-08-16 09:07:13 +02:00
Clifford Wolf	b4d544f0d9	Updated ABC to hg rev 760ba358e790	2016-08-16 00:56:42 +02:00
Clifford Wolf	4561586eed	ABC mxe cross-build fix	2016-08-16 00:52:10 +02:00
Clifford Wolf	321e15b0bf	Minor fixes in show command	2016-08-16 00:36:24 +02:00
Clifford Wolf	5d90a5b905	Added greenpak4_dffinv	2016-08-15 09:33:06 +02:00
Clifford Wolf	f0a8713fea	Fixed upto handling in verilog back-end	2016-08-15 08:26:20 +02:00
Clifford Wolf	1058660ac8	Merge pull request #200 from azonenberg/master ... Updates to GP_RCOSC, new GP_DFF*I cells	2016-08-14 15:49:08 +02:00
Andrew Zonenberg	0b0ba96488	greenpak4: Changed name of inverted output ports for consistency	2016-08-14 00:30:45 -07:00
Andrew Zonenberg	3b9756c6a3	greenpak4: Added GP_DFFxI cells	2016-08-14 00:11:44 -07:00
Andrew Zonenberg	2b062c48cb	greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)	2016-08-13 22:27:58 -07:00
Clifford Wolf	6ac67eac10	Merge pull request #198 from whitequark/master ... synth_greenpak4: use attrmvcp to move LOC from wires to cells	2016-08-11 11:17:44 +02:00
whitequark	0515809448	synth_greenpak4: use attrmvcp to move LOC from wires to cells.	2016-08-10 20:09:35 +00:00
Clifford Wolf	e9fe57c75e	Only allow posedge/negedge with 1 bit wide signals	2016-08-10 19:32:11 +02:00
Clifford Wolf	73b7232ec8	Fixed some compiler warnings in attrmap command	2016-08-10 13:44:08 +02:00
Clifford Wolf	b0aab4e304	Added "attrmap" command	2016-08-09 19:56:55 +02:00
Clifford Wolf	39da8eddae	Added log_const() API	2016-08-09 19:56:10 +02:00
Clifford Wolf	3c6d31fd06	Added "attrmvcp" pass	2016-08-09 11:18:48 +02:00
Yury Gribov	f7730d43bb	Use /proc/self/exe on Cygwin as well.	2016-08-08 12:00:27 +02:00
Clifford Wolf	9d15529214	Undo "preserve wire attributes in iopadmap" change (it was OK before)	2016-08-08 11:47:35 +02:00
Clifford Wolf	88a67afa7d	Added "test_autotb -seed" (and "autotest.sh -S")	2016-08-06 13:32:29 +02:00
Clifford Wolf	90c17aad56	preserve wire attributes in iopadmap	2016-08-06 13:24:59 +02:00
Clifford Wolf	7f755dec75	Fixed bug in parsing real constants	2016-08-06 13:16:23 +02:00
Clifford Wolf	5d6765a9d2	Added "insbuf" command	2016-08-02 10:37:19 +02:00
Clifford Wolf	21e1bac084	Merge branch 'master' of github.com:cliffordwolf/yosys	2016-07-30 12:50:39 +02:00
Clifford Wolf	5fe13a16ea	Added "write_verilog -defparam"	2016-07-30 12:46:06 +02:00
Clifford Wolf	7fa61cba1b	Added "write_verilog -nodec -nostr"	2016-07-30 12:38:40 +02:00
Clifford Wolf	da56a5bbc6	Added $initstate support to smtbmc flow	2016-07-27 16:11:37 +02:00
Clifford Wolf	8d88fcb270	Added SatGen support for $anyconst	2016-07-27 15:52:20 +02:00
Clifford Wolf	9540be1d45	Removed $predict support from SatGen	2016-07-27 15:44:11 +02:00
Clifford Wolf	4056312987	Added $anyconst and $aconst	2016-07-27 15:41:22 +02:00
Clifford Wolf	a7b0769623	Added "read_verilog -dump_rtlil"	2016-07-27 15:40:17 +02:00
Clifford Wolf	8537c4d206	Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()	2016-07-25 16:39:25 +02:00
Clifford Wolf	5b944ef11b	Fixed a verilog parser memory leak	2016-07-25 16:37:58 +02:00
Clifford Wolf	7a67add95d	Fixed parsing of empty positional cell ports	2016-07-25 12:48:03 +02:00
Clifford Wolf	b1c432af56	Improvements in CellEdgesDatabase	2016-07-24 17:21:53 +02:00
Clifford Wolf	f162b858f2	Added CellEdgesDatabase API	2016-07-24 13:59:57 +02:00
Clifford Wolf	54966679df	Moved SatHelper::setup_init() code to SatHelper::setup()	2016-07-24 12:18:39 +02:00
Clifford Wolf	34e833103b	Added $initstate support to "sat" command	2016-07-23 17:01:03 +02:00
Clifford Wolf	9aae1d1e8f	No tristate warning message for "read_verilog -lib"	2016-07-23 11:56:53 +02:00
Clifford Wolf	89deb412c6	Added satgen initstate support	2016-07-22 10:28:45 +02:00
Clifford Wolf	7fef5ff104	Using $initstate in "initial assume" and "initial assert"	2016-07-21 14:37:28 +02:00
Clifford Wolf	5c166e76e5	Added $initstate cell type and vlog function	2016-07-21 14:23:22 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Clifford Wolf	b3155af5f6	Added examples/smtbmc	2016-07-13 09:49:05 +02:00