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Code Activity
2474 commits 99 branches 53 tags 46 MiB
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Author SHA1 Message Date
Clifford Wolf
83bd27bf6e equiv_struct now creates equiv_merged attributes 2015-10-25 02:15:20 +02:00
Clifford Wolf
453736d918 Improvements in equiv_struct 2015-10-24 23:04:17 +02:00
Clifford Wolf
7f110e7018 renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() 2015-10-24 22:56:40 +02:00
Clifford Wolf
6af8076967 improvement in "stat" 2015-10-24 21:56:53 +02:00
Clifford Wolf
a1c3df7fe4 Fixed driver conflict handling (various cmds) 2015-10-24 19:23:30 +02:00
Clifford Wolf
6fe48cf41e equiv_purge bugfix, using SigChunk in Yosys namespace 2015-10-24 19:09:45 +02:00
Clifford Wolf
2a0f577f83 Fixed handling of driver-driver conflicts in wreduce 2015-10-24 13:44:35 +02:00
Clifford Wolf
4cec1c058d Added equiv_mark command 2015-10-23 23:56:58 +02:00
Clifford Wolf
c35db8c19e Disabled "Skipping blackbox module" msg in show command 2015-10-23 20:11:05 +02:00
Clifford Wolf
281a033e92 Added support for ":" as comment symbol after ;-parsing 2015-10-23 20:08:33 +02:00
Clifford Wolf
15a67392f1 Also merge $equiv cells in equiv_struct 2015-10-23 15:26:58 +02:00
Clifford Wolf
d19069b0fb Improvements in equiv_struct 2015-10-23 15:11:57 +02:00
Clifford Wolf
84a07ffb8a Added equiv_purge 2015-10-22 15:40:27 +02:00
Clifford Wolf
00e05b1310 Added equiv_struct command 2015-10-21 17:12:35 +02:00
Clifford Wolf
6416dfee93 Improved inout handling in equiv_make 2015-10-21 15:42:50 +02:00
Clifford Wolf
bbcbf739e6 Progress on cell help messages 2015-10-20 16:49:11 +02:00
Clifford Wolf
5d1c0ce7c0 Progress on cell help messages 2015-10-17 02:35:19 +02:00
Clifford Wolf
255bb914ba Progress in yosys-smtbmc 2015-10-15 15:54:59 +02:00
Clifford Wolf
5308c1e02a Fixed bug in verilog parser 2015-10-15 15:19:23 +02:00
Clifford Wolf
302166dd59 Improvements in yosys-smtbmc 2015-10-15 15:10:33 +02:00
Clifford Wolf
1d83854d84 Bugfixes in handling of "keep" attribute on wires 2015-10-15 14:57:28 +02:00
Clifford Wolf
5dd3e93e8f More "yosys-smtbmc -c" fixes 2015-10-14 23:23:25 +02:00
Clifford Wolf
9fd0f87059 Fixed yosys-smtbmc -c 2015-10-14 23:00:46 +02:00
Clifford Wolf
25c1f6e605 Added "prep" command 2015-10-14 22:46:41 +02:00
Clifford Wolf
87adb523aa Added more cell descriptions 2015-10-14 20:30:59 +02:00
Clifford Wolf
7d3a3a3173 Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Clifford Wolf
3c31572152 Added yosys-smtbmc copyright 2015-10-14 01:31:54 +02:00
Clifford Wolf
d7de0f4bd1 Improvements in yosys-smtbmc 2015-10-14 01:27:55 +02:00
Clifford Wolf
821f1b8534 Added yosys-smtbmc 2015-10-14 00:47:04 +02:00
Clifford Wolf
7bcd2a4bb3 Implemented smtbmc.py -i 2015-10-14 00:18:38 +02:00
Clifford Wolf
29160525aa Added smtbmc.py 2015-10-13 17:17:23 +02:00
Clifford Wolf
3a22b31bda Added write_smt2 -wires 2015-10-13 17:17:12 +02:00
Clifford Wolf
f42218682d Added examples/ top-level directory 2015-10-13 15:41:20 +02:00
Clifford Wolf
f13e387321 SystemVerilog also has assume(), added implicit -D FORMAL 2015-10-13 14:21:20 +02:00
Clifford Wolf
34f34be17c Merge branch 'master' of https://github.com/rubund/yosys 2015-10-13 11:01:19 +02:00
Clifford Wolf
eb1e3caae7 Fixed "flatten" for unconnected inout ports 2015-10-13 10:30:23 +02:00
Ruben Undheim
978933704b Use DESTDIR as defined in https://www.gnu.org/prep/standards/html_node/DESTDIR.html 
This is needed for painless packaging of yosys
 2015-10-11 00:56:20 +02:00
Ruben Undheim
2792b00792 Use LDFLAGS, CXXFLAGS and CPPFLAGS from the environment when building 2015-10-11 00:47:37 +02:00
Clifford Wolf
ba4cce9f19 Added support for "parameter" and "localparam" in global context 2015-10-07 14:59:08 +02:00
Clifford Wolf
e51dcc83d0 Fixed complexity of assigning to vectors in constant functions 2015-10-01 12:15:35 +02:00
Clifford Wolf
9caeadf797 Fixed detection of unconditional $readmem[hb] 2015-09-30 15:46:51 +02:00
Clifford Wolf
c58bd5dc30 Added edgetypes command 2015-09-27 11:53:20 +02:00
Clifford Wolf
281c1f4029 Some cleanups in qwp 2015-09-26 10:42:27 +02:00
Clifford Wolf
ddcfc99f8c Added "test_cell -noeval" 2015-09-25 17:27:18 +02:00
Clifford Wolf
82028c42e0 Added wreduce $mul support and fixed signed $mul opt_const bug 2015-09-25 17:27:06 +02:00
Clifford Wolf
4864736167 Bugfix in bram read-enable code 2015-09-25 14:22:33 +02:00
Clifford Wolf
f9d7df0869 Bugfixes in $readmem[hb] 2015-09-25 13:49:48 +02:00
Clifford Wolf
4ac202e2a5 Bugfixes in writing of memories as Verilog 2015-09-25 13:49:26 +02:00
Clifford Wolf
b2544cfcf7 Fixed segfault in AstNode::asReal 2015-09-25 12:38:01 +02:00
Clifford Wolf
924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00