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Author	SHA1	Message	Date
Eddie Hung	2b6cdfb39f	Move tests/various/opt* into tests/opt/	2019-08-07 21:35:48 -07:00
Eddie Hung	d5e8c0e6d3	Remove ice40_unlut call, simply do equiv_opt on synth_ice40	2019-08-07 21:33:56 -07:00
Eddie Hung	35bf509603	Add testcase from removed opt_ff.{v,ys}	2019-08-07 21:31:32 -07:00
Eddie Hung	4545bf482f	Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run	2019-08-07 16:48:38 -07:00
Eddie Hung	9776084eda	Allow whitebox modules to be overwritten	2019-08-07 16:40:24 -07:00
Eddie Hung	9962e6fc1a	Update CHANGELOG	2019-08-07 16:33:46 -07:00
Eddie Hung	675c1d4218	Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER	2019-08-07 16:29:38 -07:00
Eddie Hung	cc331cf70d	Add test	2019-08-07 16:29:38 -07:00
Eddie Hung	ea8ac8fd74	Remove ice40_unlut	2019-08-07 16:29:38 -07:00
Eddie Hung	6b314c8371	Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER	2019-08-07 16:29:38 -07:00
Eddie Hung	fb568ddb4e	Fix compile error	2019-08-07 14:31:55 -07:00
Eddie Hung	a206aed977	Run "opt_expr -fine" instead of "wreduce" due to #1213	2019-08-07 13:59:07 -07:00
Eddie Hung	d90b8b081a	Do not SigSpec::extract() beyond bounds	2019-08-07 13:58:26 -07:00
Eddie Hung	e3d898dccb	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-08-07 13:44:08 -07:00
Eddie Hung	f69410daaf	opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)	2019-08-07 13:15:02 -07:00
Eddie Hung	cdf9c80134	Do not pack registers if (* keep *)	2019-08-07 12:57:10 -07:00
Eddie Hung	3414ee1e3f	Merge pull request #1248 from YosysHQ/eddie/abc9_speedup ... abc9: speedup by using using "clean" more efficiently	2019-08-07 12:25:26 -07:00
Eddie Hung	6d77236f38	substr() -> compare()	2019-08-07 12:20:08 -07:00
Eddie Hung	71eff6f0de	RTLIL::S{0,1} -> State::S{0,1} for headers	2019-08-07 11:14:03 -07:00
Eddie Hung	7164996921	RTLIL::S{0,1} -> State::S{0,1}	2019-08-07 11:12:38 -07:00
Eddie Hung	e6d5147214	Merge remote-tracking branch 'origin/master' into eddie/cleanup	2019-08-07 11:11:50 -07:00
Eddie Hung	0c78c62d6c	Remove std:: namespace	2019-08-07 11:11:14 -07:00
Eddie Hung	13b7d2252e	'make clean' to not remove anything abc	2019-08-07 11:10:18 -07:00
Eddie Hung	48d0f99406	stoi -> atoi	2019-08-07 11:09:17 -07:00
1138-4EB	36c80cf456	dockerfile: use 'python:3-slim-buster' base image	2019-08-07 20:07:45 +02:00
1138-4EB	99de39fc79	dockerfile: use PREFIX instead of cp	2019-08-07 20:07:45 +02:00
Jim Lawson	5e8a98c8fd	Merge branch 'master' into firrtl_err_on_unsupported_cell ... # Conflicts: # backends/firrtl/firrtl.cc	2019-08-07 10:14:45 -07:00
Eddie Hung	58e512ab70	Add comment	2019-08-07 09:54:27 -07:00
Eddie Hung	f20acbc813	Revert "Add TODO" ... This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.	2019-08-07 09:54:27 -07:00
Eddie Hung	789585a744	Add TODO	2019-08-07 09:54:27 -07:00
Eddie Hung	8a8c1d7857	Compute box_lookup just once	2019-08-07 09:54:27 -07:00
Eddie Hung	03ec8d6551	Run "clean" on mapped_mod in its own design	2019-08-07 09:54:27 -07:00
Eddie Hung	3090da2d98	Run "clean -purge" on holes_module in its own design	2019-08-07 09:54:27 -07:00
David Shah	5545cd3c10	Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes ... ecp5: Make cells_sim.v consistent with nextpnr	2019-08-07 15:35:29 +01:00
Clifford Wolf	9260e97aa2	Automatically prune init attributes in verific front-end, fixes #1237 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-07 15:31:49 +02:00
David Shah	a36fd8582e	ecp5: Make cells_sim.v consistent with nextpnr ... Signed-off-by: David Shah <dave@ds0.me>	2019-08-07 14:19:31 +01:00
Clifford Wolf	e9a756aa7a	Merge pull request #1213 from YosysHQ/eddie/wreduce_add ... wreduce/opt_expr: improve width reduction for $add and $sub cells	2019-08-07 14:27:35 +02:00
David Shah	fe95807f16	[wip] DSP48E1 sim model improvements ... Signed-off-by: David Shah <dave@ds0.me>	2019-08-07 13:09:12 +01:00
Clifford Wolf	48f7682e32	Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor ... Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.	2019-08-07 12:31:32 +02:00
Clifford Wolf	4c49ddf36a	Merge pull request #1249 from mmicko/anlogic_fix ... anlogic : Fix alu mapping	2019-08-07 12:30:52 +02:00
Clifford Wolf	679bc6507f	Merge pull request #1252 from YosysHQ/clifford/fix1231 ... Fix handling of functions/tasks without top-level begin-end block	2019-08-07 12:14:54 +02:00
Clifford Wolf	c5d56fbe2d	Merge pull request #1253 from YosysHQ/clifford/check ... Be less aggressive with running design->check()	2019-08-07 12:14:41 +02:00
Clifford Wolf	f1ac998bb4	Merge pull request #1257 from YosysHQ/clifford/cellcosts ... Redesign of cell cost API	2019-08-07 12:13:50 +02:00
David Shah	607c7fa7e1	Update CHANGELOG ... Signed-off-by: David Shah <dave@ds0.me>	2019-08-07 10:56:32 +01:00
David Shah	dee8f61781	Merge pull request #1241 from YosysHQ/clifford/jsonfix ... Improved JSON attr/param encoding	2019-08-07 10:40:38 +01:00
Clifford Wolf	338f6765eb	Tweak default gate costs, cleanup "stat -tech cmos" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-07 10:25:51 +02:00
Bogdan Vukobratovic	067b44938c	Fix wrong results when opt_share called before opt_clean	2019-08-07 09:30:58 +02:00
1138-4EB	5e2919de02	dockerfile: add ARG IMAGE, use three stages	2019-08-07 05:38:09 +02:00
1138-4EB	3463511601	dockerfile: reduce number of COPY layers	2019-08-07 05:38:01 +02:00
1138-4EB	1f801993e3	dockerfile: DEBIAN_FRONTEND should not be permanent	2019-08-07 05:37:52 +02:00