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Code Activity
3248 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Clifford Wolf
126da0ad3d Fixed ice40_opt lut unmapping, added "ice40_opt -unlut" 2016-05-06 14:32:32 +02:00
Clifford Wolf
aadca148da Fixed preservation of important attributes in techmap 2016-05-06 13:59:30 +02:00
Clifford Wolf
ec1938737b Merge pull request #159 from azonenberg/master 
Fixes to use new I/O pad techmapping, renamed ports for GP_SHREG
 2016-05-05 18:18:48 +02:00
Andrew Zonenberg
2096a05ec2 Changed order of passes for better handling of INIT attributes on "output reg" FFs 2016-05-04 17:13:54 -07:00
Andrew Zonenberg
3486637b19 Changed port names in greenpak shregmap 2016-05-04 17:04:50 -07:00
Andrew Zonenberg
dee1c27a19 Renamed module parameter 2016-05-04 17:03:45 -07:00
Andrew Zonenberg
a613f171ae Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instead of extract 2016-05-04 15:55:16 -07:00
Clifford Wolf
9647dc3c07 Added tristate buffer support to iopadmap 2016-05-04 22:48:02 +02:00
Clifford Wolf
86add29072 Merge pull request #157 from azonenberg/master 
Added GP_ABUF cell, support for tri-state I/O buffers in GreenPak
 2016-05-04 19:12:59 +02:00
Andrew Zonenberg
deb1eccab5 Fixed incorrect signal naming in GP_IOBUF 2016-05-04 08:06:18 -07:00
Andrew Zonenberg
2db8dd6d35 Merge https://github.com/cliffordwolf/yosys 2016-05-04 07:23:27 -07:00
Clifford Wolf
7a74ae4c54 Merge branch 'master' of github.com:cliffordwolf/yosys 2016-05-04 10:48:42 +02:00
Clifford Wolf
658f93663b Fixed iopadmap attribute handling 2016-05-04 10:48:23 +02:00
Andrew Zonenberg
dcee3256d5 Added tri-state I/O extraction for GreenPak 2016-05-03 22:53:29 -07:00
Andrew Zonenberg
66095153fd Added GreenPak I/O buffer cells 2016-05-03 22:03:04 -07:00
Andrew Zonenberg
9fc9d5f1fb Added comment to clarify GP_ABUF cell 2016-05-02 20:29:39 -07:00
Andrew Zonenberg
79460208c9 Added GP_ABUF cell 2016-05-02 20:27:41 -07:00
Clifford Wolf
12000b90de Merge pull request #154 from azonenberg/master 
Add GP_PGA cell
 2016-05-02 09:49:07 +02:00
Andrew Zonenberg
3a85e40f42 Merge https://github.com/cliffordwolf/yosys 2016-05-01 10:07:21 -07:00
Clifford Wolf
06d35ea942 Improved TCL_VERSION detection so it does not read .tclshrc 2016-04-29 10:26:22 +02:00
Andrew Zonenberg
fb87022dca Merge https://github.com/cliffordwolf/yosys 2016-04-29 00:57:37 -07:00
Clifford Wolf
e01464e2ac Added "qwp -v" 2016-04-28 23:17:30 +02:00
Andrew Zonenberg
134e093e4e Added GP_PGA cell 2016-04-27 23:07:21 -07:00
Clifford Wolf
0d2923cccd Connections between inputs and inouts are driven by the input 2016-04-26 19:49:05 +02:00
Clifford Wolf
958fb29c76 Fixed test_autotb for modules with many cell ports 2016-04-25 16:37:11 +02:00
Clifford Wolf
93e107e455 Fixed proc_mux performance bug 2016-04-25 10:43:04 +02:00
Clifford Wolf
d086224a39 Merge pull request #150 from azonenberg/master 
GreenPak analog comparator support
 2016-04-25 10:33:18 +02:00
Andrew Zonenberg
d57c85111f Merge https://github.com/cliffordwolf/yosys 2016-04-24 22:11:56 -07:00
Andrew Zonenberg
349d717202 Removed VIN_BUF_EN 2016-04-24 17:01:21 -07:00
Clifford Wolf
b1d6f05fa2 Fixed performance bug in proc_dlatch 2016-04-24 19:29:56 +02:00
Clifford Wolf
9aa4b3309c Added "yosys -D ALL" 2016-04-24 17:12:34 +02:00
Andrew Zonenberg
6e215f374d Renamed VOUT to OUT on GP_ACMP cell 2016-04-23 22:53:49 -07:00
Andrew Zonenberg
512486dcf3 Added GP_ACMP cell 2016-04-23 22:33:36 -07:00
Clifford Wolf
09ffebb995 Added "prep -flatten" and "synth -flatten" 2016-04-24 00:48:33 +02:00
Clifford Wolf
77aa2031e7 Converted "prep" to ScriptPass 2016-04-24 00:48:06 +02:00
Clifford Wolf
096c25d29d Improvements in greenpak4 shreg mapping 2016-04-23 23:10:13 +02:00
Clifford Wolf
c9c5192cd6 Run clean after splitnets in synth_greenpak4 2016-04-23 23:09:45 +02:00
Andrew Zonenberg
7f16784f3c Merge https://github.com/cliffordwolf/yosys 2016-04-23 12:22:08 -07:00
Clifford Wolf
e13c66122e Added "shregmap -zinit" for greenpak4 tech 2016-04-23 20:20:21 +02:00
Andrew Zonenberg
421b0d715c Merge https://github.com/cliffordwolf/yosys 2016-04-23 10:18:15 -07:00
Clifford Wolf
34195f281f Merge https://github.com/azonenberg/yosys 2016-04-23 10:33:32 +02:00
Clifford Wolf
f85cfa5666 Added "shregmap" to synth_greenpak4 2016-04-23 10:31:19 +02:00
Clifford Wolf
a24021ea20 Converted synth_greenpak4 to ScriptPass 2016-04-23 10:27:33 +02:00
Andrew Zonenberg
2849fd486e Fixed typo in help text 2016-04-22 23:01:39 -07:00
Andrew Zonenberg
0cbe70eaa4 Fixed typo 2016-04-22 19:08:19 -07:00
Andrew Zonenberg
ab11f2aa70 Merge https://github.com/cliffordwolf/yosys 2016-04-22 19:07:55 -07:00
Clifford Wolf
7311be4028 Added "shregmap -tech greenpak4" 2016-04-22 19:42:08 +02:00
Clifford Wolf
779e2cc819 Added support for "active high" and "active low" latches in BLIF front-end 2016-04-22 18:02:55 +02:00
Clifford Wolf
60ac1bd178 Added support for "active high" and "active low" latches in BLIF back-end 2016-04-22 18:00:46 +02:00
Clifford Wolf
965b0d59b5 More flexible handling of initialization values 2016-04-22 12:13:06 +02:00