Rupert Swarbrick
7ff306ccdb
Minor optimisation in Module::wire() and Module::cell()
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The existing code does a search to figure out whether id is in the
dict (with the call to count()), and then looks it up again to get the
result (with the call to at()). This version calls find() instead,
avoiding the double lookup.
Code size increases slightly (6kb). I think this is because the
contents of find() are getting inlined, and then inlined into lots of
the callsites for cell() and wire().
Looking at the compiled code before this patch, you just get
a (non-inlined) call to count() followed by a call to at(). After the
patch, the contents of find() have been inlined (so you see do_hash,
then do_lookup). The result for each function is about 30 bytes / 40%
bigger, which presumably also enlarges call-sites that inline it.
2020-05-26 16:07:36 +01:00
Eddie Hung
a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
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xilinx: tidy up cells_sim.v a little
2020-05-25 14:21:10 -07:00
Eddie Hung
08221edbc1
tests: xilinx macc test to have initval, shorten BMC depth for runtime
2020-05-25 10:09:05 -07:00
Eddie Hung
5b81df57c8
xilinx: tidy up cells_sim.v a little
2020-05-25 09:48:11 -07:00
Eddie Hung
59b355fb85
Merge pull request #2044 from YosysHQ/eddie/fix2037
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verilog: allow attributes on behavioural statements (including null statement)
2020-05-25 09:14:00 -07:00
Eddie Hung
c5a9abba11
verilog: move attr from simple_behav_stmt to its children to attach
2020-05-25 07:36:53 -07:00
Eddie Hung
95dcd7e785
test: add attribute-before-stmt test from @nakengelhardt
2020-05-25 07:36:53 -07:00
Eddie Hung
1c117ac023
verilog: do not warn for attributes on null statements
2020-05-25 07:36:53 -07:00
Eddie Hung
29d84339bf
tests: add an generate-else test too
2020-05-25 07:36:53 -07:00
Eddie Hung
88bddb37c9
verilog: handle empty generate statement by removing gen_stmt_or_null...
...
... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
2020-05-25 07:36:53 -07:00
Eddie Hung
d21a07c7b5
verilog: fix #2037 by permitting (and freeing) attributes on null stmt
2020-05-25 07:36:53 -07:00
Eddie Hung
589775538c
tests: add #2037 testcase
2020-05-25 07:36:53 -07:00
clairexen
ae11156c90
Merge pull request #2015 from boqwxp/qbfsat-bisection
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qbfsat: Add an iterative bisection optimization method and make it the default.
2020-05-25 15:50:18 +02:00
Eddie Hung
89ed34fe55
Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanup
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xaiger: do not derive cells
2020-05-24 10:10:50 -07:00
Eddie Hung
33b03ce904
xaiger: add testcase
2020-05-24 08:48:23 -07:00
Eddie Hung
d64df21630
xaiger: do not derive cells
2020-05-24 08:17:30 -07:00
Eddie Hung
227c3ff310
Merge pull request #2074 from YosysHQ/eddie/ecp5_cleanup
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ecp5: cleanup unused +/ecp5/abc9_model.v
2020-05-23 09:28:42 -07:00
Eddie Hung
76e0cc8276
ecp5: cleanup unused +/ecp5/abc9_model.v
2020-05-23 08:17:40 -07:00
Alberto Gonzalez
ac41f8a9c7
qbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d6.
2020-05-23 00:53:09 +00:00
Alberto Gonzalez
aea0fd5ed4
qbfsat: Add bisection mode and make it the default.
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Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.
2020-05-23 00:53:09 +00:00
whitequark
721040df76
Merge pull request #2072 from whitequark/cxxrtl-dont-purge
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cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level
2020-05-22 20:08:39 +00:00
whitequark
281c96856a
cxxrtl: get rid of -O5 aka opt_clean -purge optimization level.
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This isn't actually necessary anymore after scheduling was improved,
and `clean -purge` disrupts the mapping between wires in the input
RTLIL netlist and the output CXXRTL code.
2020-05-22 19:08:30 +00:00
Eddie Hung
4f0f321169
abc9_ops: update comment
2020-05-21 21:39:13 -07:00
Eddie Hung
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
Eddie Hung
38e858af8d
Update frontends/verilog/verilog_parser.y
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Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-05-21 09:10:56 -07:00
Miodrag Milanović
637650597b
Merge pull request #2059 from boqwxp/logger-vector-to-dict
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log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-21 15:36:30 +02:00
N. Engelhardt
026fed3135
Merge pull request #2046 from PeterCrozier/trap
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Extend YS_DEBUGTRAP to MacOS.
2020-05-20 10:12:24 +02:00
N. Engelhardt
7c4e580f8f
Merge pull request #2054 from boqwxp/fix-smtbmc
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smtbmc: Fix return status handling.
2020-05-20 08:55:36 +02:00
Alberto Gonzalez
1053032a81
smtbmc: Fix typo in error message.
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Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-05-19 16:13:44 +00:00
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
Eddie Hung
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
Claire Wolf
fa8cb3e35d
Revert "Add support for non-power-of-two mem chunks in verific importer"
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This reverts commit 173aa27ca5
2020-05-17 11:31:11 +02:00
Alberto Gonzalez
8297afe925
log: Use dict instead of std::vector<std::pair> for log_expect_{error, warning, log} to better express the intent that each element is unique.
2020-05-15 00:55:32 +00:00
Eddie Hung
67fc0c3698
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
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instead of moving them to $__ prefix
2020-05-14 16:44:35 -07:00
Eddie Hung
7101ef550b
verilog: attributes before task enable (but 13 s/r conflicts)
2020-05-14 16:10:11 -07:00
Eddie Hung
e7fd8912f0
tests: attributes before task enable
2020-05-14 16:09:41 -07:00
Eddie Hung
07eecff9cc
Merge pull request #2055 from YosysHQ/eddie/logger_multiple
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logger: fix for multiple calls with same pattern
2020-05-14 15:30:08 -07:00
Eddie Hung
7b3a4a1fff
opt_expr: Sx to Sz; spotted by @Xiretza
2020-05-14 12:14:23 -07:00
Eddie Hung
73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
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opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-05-14 11:56:22 -07:00
Eddie Hung
425867d175
logger: clean up doc
2020-05-14 10:38:31 -07:00
Eddie Hung
02df0198b6
abc9_ops: -prep_hier to create unmap module that removes Q's (* init *)
2020-05-14 10:33:57 -07:00
Eddie Hung
13f9d65b6f
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
2020-05-14 10:33:57 -07:00
Eddie Hung
fa31e84112
Fix broken test when ignoring abc9_flop with init == 1'b1
2020-05-14 10:33:57 -07:00
Eddie Hung
97a0a04314
abc9_ops/xaiger: further reducing Module::derive() calls by ...
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replacing _all_ (* abc9_box *) instantiations with their derived types
2020-05-14 10:33:57 -07:00
Eddie Hung
e79127fceb
Cleanup; reduce Module::derive() calls
2020-05-14 10:33:57 -07:00
Eddie Hung
cea614f5ae
ecp5: latches_map.v if *not* -asyncprld
2020-05-14 10:33:57 -07:00
Eddie Hung
fdc340db8e
ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v
2020-05-14 10:33:57 -07:00
Eddie Hung
39759d5f0e
ecp5: fix rebase mistake
2020-05-14 10:33:57 -07:00
Eddie Hung
8d34aee3d5
abc9: update to =_$abc9_flops pattern which includes whiteboxes
2020-05-14 10:33:57 -07:00
Eddie Hung
f652a9c11c
abc9_ops: update docs
2020-05-14 10:33:57 -07:00
