Dan Ravensloft
3b534a203a
intel_alm: fix typo in MISTRAL_MUL27X27 cell name
2020-08-13 17:08:50 +02:00
Dan Ravensloft
97daf612cb
intel_alm: add more megafunctions. NFC.
2020-08-12 18:39:22 +02:00
Marcelina Kościelnicka
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
Dan Ravensloft
a2fb84fd0c
intel_alm: direct M10K instantiation
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This reverts commit a3a90f6377
2020-07-27 15:39:06 +02:00
Dan Ravensloft
62311b7ec0
intel_alm: increase abc9 -W
2020-07-26 23:56:54 +02:00
Dan Ravensloft
4d9d90079c
intel_alm: add additional ABC9 timings
2020-07-23 11:57:07 +01:00
Lofty
a3a90f6377
Revert "intel_alm: direct M10K instantiation"
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This reverts commit 09ecb9b2cf
2020-07-13 18:05:38 +02:00
Dan Ravensloft
09ecb9b2cf
intel_alm: direct M10K instantiation
2020-07-05 23:28:59 +02:00
Dan Ravensloft
b004f09018
intel_alm: DSP inference
2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka
3ca2de0f77
synth_intel_alm: Use dfflegalize.
2020-07-04 22:56:16 +02:00
Dan Ravensloft
c6765443fd
Improve MISTRAL_FF specify rules
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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2020-07-04 19:45:10 +02:00
Eddie Hung
2bdced0d68
intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
2020-07-04 19:45:10 +02:00
Eddie Hung
3db3e1e149
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
2020-07-04 19:45:10 +02:00
Dan Ravensloft
83cde2d02b
intel_alm: ABC9 sequential optimisations
2020-07-04 19:45:10 +02:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Dan Ravensloft
8b4eb78849
intel_alm: fix DFFE matching
2020-06-11 19:55:51 +02:00
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
Eddie Hung
8fbb55f4ab
synth_*: no need to explicitly read +/abc9_model.v
2020-05-14 10:33:56 -07:00
Dan Ravensloft
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
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By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
Dan Ravensloft
4ca5f9799b
intel_alm: cleanup duplication
2020-04-24 11:26:48 +02:00
Dan Ravensloft
3d149aff73
intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00
Dan Ravensloft
16a3048308
intel_alm: Documentation improvements
2020-04-21 19:38:15 +02:00
Dan Ravensloft
43cc6bd8a1
synth_intel_alm: VQM support
2020-04-15 16:15:25 +02:00
Dan Ravensloft
2e37e62e6b
synth_intel_alm: alternative synthesis for Intel FPGAs
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By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
