Krystine Sherwin
7f12d0ba95
QLF_TDP36K: more basic tdp/sdp sim tests
...
Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
2023-12-04 15:52:03 +01:00
Krystine Sherwin
3d08ed216d
QLF_TDP36K: parameterised sim test gen
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Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ba3be3fd1c
QLF_TDP36K: test bram_tdp post synth
2023-12-04 15:52:03 +01:00
N. Engelhardt
f9c8978128
add example memory test
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ede4eaeee2
quicklogic: wildcard asymmetric memory tests
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ba09866217
quicklogic: testing port widths on split rams
2023-12-04 15:52:03 +01:00
Krystine Sherwin
1a843b2a86
quicklogic: testing 1:4 assymetric memory
2023-12-04 15:52:03 +01:00
Krystine Sherwin
7513bfcbfe
quicklogic: fix double width read
2023-12-04 15:52:03 +01:00
Krystine Sherwin
8d3b238b9b
quicklogic: Testing split TDP36K
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Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
991850e1c9
quicklogic: Initial blockram tests
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Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
2023-12-04 15:52:03 +01:00
Martin Povišer
a5c8d246f7
quicklogic: Add k6n10f DSP test
2023-12-04 15:52:03 +01:00
Martin Povišer
db9e5b4f14
quicklogic: Fix dffs.ys test
2023-12-04 15:52:03 +01:00
Martin Povišer
554d8caef7
quicklogic: Add basic k6n10f tests
2023-12-04 15:52:03 +01:00
Martin Povišer
6672b6c1b3
quicklogic: Move pp3 tests one level down
2023-12-04 15:52:02 +01:00
N. Engelhardt
98769010af
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
Martin Povišer
62d6338688
quicklogic: Fix pp3 dffs test
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Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
2023-10-12 12:45:40 +02:00
Lofty
dce037a62c
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
Marcelina Kościelnicka
4a35f244aa
quicklogic: Add .gitignore file for test outputs.
2021-03-23 17:35:00 +01:00
Lofty
f4298b057a
quicklogic: PolarPro 3 support
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Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
